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Subsequently, x-boot loads the images of TF-A (BL31), OP-TEE (BL32), and U-Boot (BL33) from a storage device into DRAM. The CPU (core 0) then switches itself from 32-bit mode to 64-bit by triggering a software reset. It proceeds to awaken other cores (core 1, 2, 3) and transitions them to 64-bit mode. Finally, all cores execute TF-A.
Table of Contents
| Table of Contents |
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Features
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The flow chart below illustrates the process from i-boot's reset vector to the jump to TF-A for all cores
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Source
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Files
The source files for x-boot are located in the "boot/xobot/" directory under the project's top folder. The entry point for x-boot is the label "_start" in the assembly file "arch/arm/sp7350/start.S". Notably, "_start" is situated at an offset of 32 bytes within the x-boot module, with the initial 32-byte space reserved for a header. The "_start" subroutine initializes the C execution environment and subsequently jumps to the C main function, the "xboot_main()" subroutine in the "xboot.c" file. The "xboot.c" file serves as the top-level control file for x-boot, governing the entire flow of operations.
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Files or folders | Descriptions |
adc/ | Contains subroutines for ADC. |
arch/arm/sp7350/ | Houses CPU-relevant codes, including:
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bin/ | Output folder |
common/ | Contains common code, such as verifying images. |
configs/ | Contains defconfig files for boards. |
cpio/ | Contains CPIO codes. |
draminit/ | Contains DRAM-related codes. |
fat/ | Contains codes for FAT file-system operations. |
i2c/ | Contains subroutines for I2C interface. |
include/ | Contains many constant definitions used in x-boot. |
lib/ | Contains images CRC verification codes. |
nand/ | Contains SPI-NAND and 8-bit NAND drivers. |
otp/ | Contains subroutines for accessing OTP. |
romshare/ | Contains the entry table for accessing secure functions in i-boot. |
sdmmc/ | Contains SD card and eMMC drivers. |
tools/ | Contains some utilities used by x-boot. |
usb/ | Contains USB2.0 and USB3.0 drivers. |
warmboot/ | Contains a concise version of x-boot for running during warm-boot. |
Kconfig | Menu config file of x-boot. |
Makefile | Make file of x-boot |
xboot.c | Main C file of x-boot. |
Driver
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Specifications and
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Features
x-boot incorporates a range of device drivers, each offering specific features to facilitate various operations. The following table outlines the detailed specifications and features of these drivers.
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During system boot, i-boot reads boot-related information from the boot switch and the OTP (One-Time Programmable) memory within the chip. This information is then stored in the C structure g_bootinfo. x-boot directly utilizes the data in the g_bootinfo structure to determine the boot mode and process.
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x-boot Log and
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Explanation
Line 1: Banner (version) of x-boot
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Line 79-81: Loading fip image (including TF-A and OP-TEE images). Size of fip image is 408,462 bytes. The checksum of fip image is successfully verified.
Line 8382: Loaded uboot image is loaded at 0x00500040.
Line 83: fip image is loaded at 0x01000000.
Line 84: Initializing Cortex M4 hardware. Reset of CM4 is asserted here.
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| Code Block |
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+++xBoot Feb 14 2024 18:41:41
Remap DRAM for 4GB
ID1 of STI8070X = 0x88
ID2 of STI8070X = 0x01
Set PLLC to 1.5GHz
Set PLLL3 to 1.2GHz
PLLD: 800MHz, DATARATE:3200
0x00001008
0x0000C0BE
0x00000107
[d] xboot.c :397
..mode=0x0000001F
{{emmc_boot}}
[d] common/bootmain.c :76
dev=2
pin=1
.Run draiminit@0xFA208351
bootdevice=0x0000001F
Built at Feb 14 2024 18:41:37
dram_init
dwc_umctl2_lpddr4_1600_SP7350_for_realchip
MT53E1G32D2_B, 2rank, FBGA=D8CJG
SDRAM_SPEED_1600
dwc_ddrphy_phyinit_main 20231212
dwc_ddrphy_phyinit_out_lpddr4_train1d2d_3200_SP7350
bootdevice:0x0000001F
XBOOT_len=0x0000AEA0
1D IMEM checksum ok
1D DMEM checksum ok
Start to wait for the training firmware to complete v.00 !!!
End of CA training.
End of initialization.
End of read enable training.
End of fine write leveling.
End of read dq deskew training.
End of MPR read delay center optimization.
End of Wrtie leveling coarse delay.
End of write delay center optimization.
End of read delay center optimization.
End of max read latency training.
Training has run successfully.(firmware complete)
bootdevice:0x0000001F
2D IMEM checksum ok
2D DMEM checksum ok
Start to wait for the training firmware to complete v.00 !!!
End of initialization.
End of 2D write delay/voltage center optimization.
End of 2D write delay/voltage center optimization.
End of 2D read delay/voltage center optimization.
End of 2D read delay/voltage center optimization.
Training has run successfully.(firmware complete)
Register programming done!!!
Register programming done!!!
dram_init_end
Done draiminit
dram test 0x00800000 - 0x00800400
Set WL_REG_ON (GPIO56) to HI.
[d] sdmmc/drv_sd_mmc.c :21
InitChipCtrl
busclk=200000
div=1789
[d] sdmmc/drv_sd_mmc.c :23
IdentifyStorage
[d] sdmmc/hal_sd_mmc.c :507
busclk=25000000
div=14
[d] sdmmc/hal_sd_mmc.c :1729
[d] sdmmc/drv_sd_mmc.c :33
Read GPT
part1 LBA=0x00000022
emmc load uboot@blk=0x00000022
uboot1 hdr good
part2 LBA=0x00000822
emmc load uboot@blk=0x00000822
data size=858952
verify img...
uboot2 good
emmc load fip@blk=0x00001022
data size=408462
verify img...
uboot_pentagram_board
Loaded uboot@0x00500040 @0x00500040
fip @0x01000000
M4 init:
32->64
a64up@0xFA218400
core0 S-EL3 @0x00200000 |
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