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Following this initialization phase, i-boot loads x-boot from external storage devices into SRAM and performs a checksum verification. If the verification passes, i-boot proceeds to execute x-boot.

Table of Contents

Table of Contents

Key

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Features

  1. Output log at UART0 with a baud rate of 115,200 bps.

  2. UART0 pins can be turned off through an OTP bit.

  3. Read bootstrap pins IV_MX[6..3] to decide boot-device.

  4. Support for five boot devices: SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card, and USB flash drive (on either USB2.0 or USB3.0 port).

  5. Implementation of secure-boot with the ability to verify the digital signature of the x-boot image and decrypt it.

  6. Secure-boot activation controlled by an OTP bit.

  7. Support for warm-boot, enabling wake-up from deep-sleep mode.

  8. Support for the peripheral-reset signal (output from G_MX2).

Main

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Flow

The i-boot flow initiates with the reset vector, followed by the execution of the "cpu_init" subroutine responsible for initializing the CPU. Next in the sequence is the "start_boot" subroutine, which sets up the C execution environment. The flow then advances to execute the "iboot_main" subroutine, serving as the C main function within i-boot.

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It's essential to note that i-boot does not initialize DDR DRAM, rendering it temporarily unavailable. Hence, x-boot must be loaded into SRAM for execution.

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Boot

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Devices

i-Boot supports five boot devices, each with specific specifications and requirements. Below is a detailed table outlining the specifications for each boot device:

Boot devices

Specifications

8-bit NAND

flash

  1. The first block should contain Sunplus Boot Profile Header.

  2. x-boot image should be stored in 1K60 ECC sectors.

  3. x-boot image should be stored in 1K60 ECC sectors.

  4. Set read cycle-time to 240 nS.

  5. GPIO82 set to HIGH for 3.0V NAND flash, LOW for 1.8V NAND flash.

eMMC device

  1. x-boot image should be stored at Boot Area Partition 1.

  2. Set bus clock to 25 MHz.

  3. GPIO82 set to HIGH for 3.0V IO power, LOW for 1.8V IO power.

SPI-NAND flash

  1. First block should contain Sunplus Boot Profile Header.

  2. x-boot image should be stored in 1K60 ECC sectors.

  3. Support for X1 and X2 positions. Attempt X1 position first and then proceed to X2 position.

  4. Set bus clock to 11.2 MHz.

  5. GPIO82 set to HIGH for 3.0V SPI-NAND flash, LOW for 1.8V SPI-NAND flash.

SPI-NOR flash

  1. x-boot image should be stored at offset 0x18000 (96KiB).

  2. Set bus clock to 11.2 MHz.

  3. GPIO82 set to HIGH for 3.0V SPI-NOR flash, LOW for 1.8V SPI-NOR.

SD card

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. ISPBOOOT.BIN should be stored in the root directory of the first or sole partition of the SD card.

  3. The partition should be formatted to FAT32 or FAT16 file-system.

  4. Set bus clock to 5 MHz.

USB flash drive

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. ISPBOOOT.BIN should be stored in the root directory of first or sole partition of the USB flash drive.

  3. The partition should be formatted to FAT32 or FAT16 file-system.

  4. Support high-speed only

  5. Support USB flash drive on both USB2.0 or USB3.0 ports. Attempt USB3.0 port first and then proceed to USB2.0 port.

CPU

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Boot Core and Other Cores

CPU core 0 serves as the boot core, responsible for all boot processes from i-boot to Linux. Meanwhile, CPU core 1, 2, and 3 enter a spin state (wfe mode) within i-boot after self-initialization, awaiting activation by core 0. The subsequent assembly code illustrates these processes.

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CPU core 0 fills the specified value into the CPU Run Control field of the target core to wake it up.

Bootstrap

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Pins of SP7350

The state of bootstrap pins of SP7350 is read into bootstrap register (G0.31) upon releasing power-on reset. Refer to definition of boot-strap pins in i-boot below:

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  1. If MX1 = 0, the JTAG interface of CA55 of SP7350 will be enabled.

  2. If MX2 = 0, SP7350 will enter test mode. Always set to 1 for normal operation.

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i-boot Log and

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Explanation

Line 1: Banner The banner (version) of i-boot

Line 4: Boot-mode is 0x1F (MX[6..2]), indicating eMMC boot.

Line 6: “[emmc_boot]” signifies that i-boot is executing the 'emmc boot' flow.

Line 11: The bus clock of eMMC is configured to 200kHz (divisor = 1789) for the IdentifyStorage command.

Line 15: The bus clock of eMMC is adjusted to 25MHz (divisor = 14) for subsequent Read and other commands.

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Line 25: The length of the x-boot image is 0xAE38 0xAEA0 (44,600 704 bytes), excluding DDR training firmware.

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Code Block
+++iBoot v1.0 Oct 18 2022 13:51:18
[d] iboot.c:134
[d] iboot.c:157
mode=0x0000001F

[emmc_boot]
dev=2 pin=1
.[d] bootmain.c:136
...[d] drv_sd_mmc.c:21
InitChipCtrl
busclk=200000 div=1789
[d] drv_sd_mmc.c:23
IdentifyStorage
[d] hal_sd_mmc.c:478
busclk=25000000 div=14
[d] hal_sd_mmc.c:1709
[d] drv_sd_mmc.c:33
[d] iboot.c:526
mg=0x54554258
len=0x0000AE380x0000AEA0
chk=0x000028660x0000F3D7
[d] iboot.c:557
[d] iboot.c:567
mg=0x54554258
len=0x0000AE380x0000AEA0
chk=0x000028660x0000F3D7
flg=0x00000000
[d] bootmain.c:559
img chksum correct

boot!
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