This article provides a brief overview of the SP7350 software. Subsequent articles will delve into the detailed components of the software. The initial section begins with an introduction to source code and software operations, followed by an explanation of CPU addressing space. The final section touches on the device address map.
Table of Contents
| Table of Contents |
|---|
Source Code
The source code for SP7350 is readily available on both GitHub and Gitee repositories:
GitHub: SP7350 Source Code
Gitee: SP7350 Source Code
For downloading and compiling the code, detailed instructions can be found at:
https://sunplus.atlassian.net/wiki/x/1gB-dg
Additionally, for in-system programming of flash devices on the SP7350 platform, refer to:
https://sunplus.atlassian.net/wiki/x/b4Djdg
Software Operations
The software components include i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux, and FreeRTOS. The operation flow of these components is illustrated in the figure below:
...
Bit | Descriptions | Hardware Name | Level/Edge |
0 | Interrupt_from_GPIO | PI_GPIO_INT0 | Programmable |
1 | Interrupt_from_GPIO | PI_GPIO_INT1 | Programmable |
2 | Interrupt_from_GPIO | PI_GPIO_INT2 | Programmable |
3 | Interrupt_from_GPIO | PI_GPIO_INT3 | Programmable |
4 | Interrupt_from_GPIO | PI_GPIO_INT4 | Programmable |
5 | Interrupt_from_GPIO | PI_GPIO_INT5 | Programmable |
6 | Interrupt_from_GPIO | PI_GPIO_INT6 | Programmable |
7 | Interrupt_from_GPIO | PI_GPIO_INT7 | Programmable |
8 | I2C0 | I2C0_INT | Level |
9 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT0 | Level |
10 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT1 | Level |
11 | RTC_2Hz_INT_to_CM4 | RTC_2HZ_INT | Edge |
12 | CPIOR | CPIOR_CTL_INT | Level |
13 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT2 | Level |
14 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT3 | Level |
15 | SDIO_controller | CARD_CTL2_INT | Level |
16 | SD_controller | CARD_CTL1_INT | Level |
17 | EMMC_controller | CARD_CTL0_INT | Level |
18 | SPI_FLASH | SPI_INT | Level |
19 | GMAC | GMAC_INT | Level |
20 | AXI_DMA | AXI_DMA_INT | Level |
21 | GMAC | GMAC_PMT_INT | Level |
22 | I2C6 | I2C6_INT | Level |
23 | SPI_NAND | SPI_ND_INT | Level |
24 | BCH | BCH_INT | Level |
25 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT4 | Level |
26 | MAILBOX0_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT5 | Level |
27 | SPI_CB0 | SPI_CB0_INT | level |
28 | SPI_CB1 | SPI_CB1_INT | level |
29 | SPI_CB2 | SPI_CB2_INT | level |
30 | SPI_CB3 | SPI_CB3_INT | level |
31 | SPI_CB4 | SPI_CB4_INT | level |
32 | SPI_CB5 | SPI_CB5_INT | level |
33 | THERMAL | THERMAL_S_INT | Level |
34 | THERMAL | THERMAL_A_INT | Level |
35 | UART2AXI | UADBG_INT | Level |
36 | VI0_CSIIW0 | VI0_CSIIW0_INT_FIELD_START | Level |
37 | VI0_CSIIW0 | VI0_CSIIW0_INT_FIELD_END | Level |
38 | VI0_CSIIW1 | VI0_CSIIW1_INT_FIELD_START | Level |
39 | VI0_CSIIW1 | VI0_CSIIW1_INT_FIELD_END | Level |
40 | VI1_CSIIW0 | VI1_CSIIW0_INT_FIELD_START | Level |
41 | VI1_CSIIW0 | VI1_CSIIW0_INT_FIELD_END | Level |
42 | VI1_CSIIW1 | VI1_CSIIW1_INT_FIELD_START | Level |
43 | VI1_CSIIW1 | VI1_CSIIW1_INT_FIELD_END | Level |
44 | VI4_CSIIW0 | VI4_CSIIW0_INT_FIELD_START | Level |
45 | VI4_CSIIW0 | VI4_CSIIW0_INT_FIELD_END | Level |
46 | VI4_CSIIW1 | VI4_CSIIW1_INT_FIELD_START | Level |
47 | VI4_CSIIW1 | VI4_CSIIW1_INT_FIELD_END | Level |
48 | SEC_IP | SEC_INT | Level |
49 | AXI_Global_Monitor_int | AXI_MON_TOP_INT | Level |
50 | AXI_Global_Monitor_int | AXI_MON_PAI_INT | Level |
51 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMERW | Level |
52 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER0 | Edge |
53 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER1 | Edge |
54 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER2B | Edge |
55 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER3B | Edge |
56 | RTC | WakeupKey_INT | Level |
57 | TZC400 | TZC_400_INT | Level |
58 | GMAC | GMAC_LPI_INT | Level |
59 | MIPITX | MIPITX_INT | Level |
60 | UART | UA0_INT | Level |
61 | UART | UA1_INT | Level |
62 | Reserved | AXI_MON_TOP_INT | Level |
63 | DISP_PWM | DISP_PWM_USER_INT_0 | Edge |
64 | DISP_PWM | DISP_PWM_INT_END_0 | Edge |
65 | DISP_PWM | DISP_PWM_USER_INT_1 | Edge |
66 | DISP_PWM | DISP_PWM_INT_END_1 | Edge |
67 | DISP_PWM | DISP_PWM_USER_INT_2 | Edge |
68 | DISP_PWM | DISP_PWM_INT_END_2 | Edge |
69 | DISP_PWM | DISP_PWM_USER_INT_3 | Edge |
70 | DISP_PWM | DISP_PWM_INT_END_3 | Edge |
71 | PNAND | PNAND_INT | level |
72 | RBUS_in_AO | RBUS_INTERRUPT | Level |
73 | Reserved | AXI_MON_PAI_INT | Level |
74 | CB_DMA0 | CBDMA0_INT | Level |
75 | Reserved | AXI_MON_PAII_INT | Level |
76 | RBUS | RBUS_INTERRUPT | Level |
77 | VC8000E | VCE_INT | Level |
78 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT6 | Level |
79 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT7 | Level |
80 | VI23_CSIIW0 | VI23_CSIIW0_INT_FIELD_START | Level |
81 | VI23_CSIIW0 | VI23_CSIIW0_INT_FIELD_END | Level |
82 | VI23_CSIIW1 | VI23_CSIIW1_INT_FIELD_START | Level |
83 | VI23_CSIIW1 | VI23_CSIIW1_INT_FIELD_END | Level |
84 | VI23_CSIIW2 | VI23_CSIIW2_INT_FIELD_START | Level |
85 | VI23_CSIIW2 | VI23_CSIIW2_INT_FIELD_END | Level |
86 | VI23_CSIIW3 | VI23_CSIIW3_INT_FIELD_START | Level |
87 | VI23_CSIIW3 | VI23_CSIIW3_INT_FIELD_END | Level |
88 | VCL | VCL_INTR0 | Level |
89 | VCL | VCL_INTR1 | Level |
90 | VCL | VCL_INTR2 | Level |
91 | VCL | VCL_INTR3 | Level |
92 | VCL | VCL_INTR4 | Level |
93 | VCL | VCL_INTR5 | Level |
94 | I2C1 | I2C1_INT | Level |
95 | I2C2 | I2C2_INT | Level |
96 | I2C3 | I2C3_INT | Level |
97 | I2C4 | I2C4_INT | Level |
98 | I2C5 | I2C5_INT | Level |
99 | RTC | RTC_PERIODIC_INT | Edge |
100 | AUD | LOSD_INT | Edge |
101 | AUD | AUD_FIFO_INT | Level |
102 | AUD | AUD_TWS_LATCH_INT | Level |
103 | AUD | AUD_TWS_SAMPLE_INT | Level |
104 | TGEN | TGEN_INT_FIELD_START | Edge |
105 | TGEN | TGEN_INT_FIELD_END | Edge |
106 | TGEN | TGEN_INT_USER1 | Edge |
107 | TGEN | TGEN_INT_USER2 | Edge |
108 | VCL | VCL_INTR6 | Edge |
109 | VCL | VCL_INTR7 | Level |
110 | I2C7 | I2C7_INT | Level |
111 | I2C8 | I2C8_INT | Level |
112 | PNAND | PNAND_ERROR_INT | level |
113 | STC_AV3 | STC_AV3_INTERRUPT_TIMERW | Level |
114 | STC_AV3 | STC_AV3_INTERRUPT_TIMER0 | Edge |
115 | STC_AV3 | STC_AV3_INTERRUPT_TIMER1 | Edge |
116 | STC_AV3 | STC_AV3_INTERRUPT_TIMER2B | Edge |
117 | STC_AV3 | STC_AV3_INTERRUPT_TIMER3B | Edge |
118 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT0 | Level |
119 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT1 | Level |
120 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT2 | Level |
121 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT3 | Level |
122 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT4 | Level |
123 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT5 | Level |
124 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT6 | Level |
125 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT7 | Level |
126 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_INT | Level |
127 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_INT | Level |
128 | STC | STC_INTERRUPT_TIMERW | Level |
129 | STC | STC_INTERRUPT_TIMER0 | Edge |
130 | STC | STC_INTERRUPT_TIMER1 | Edge |
131 | STC | STC_INTERRUPT_TIMER2B | Edge |
132 | STC | STC_INTERRUPT_TIMER3B | Edge |
133 | STC_AV0 | STC_AV0_INTERRUPT_TIMER0 | Edge |
134 | STC_AV0 | STC_AV0_INTERRUPT_TIMER1 | Edge |
135 | STC_AV0 | STC_AV0_INTERRUPT_TIMER2B | Edge |
136 | STC_AV0 | STC_AV0_INTERRUPT_TIMER3B | Edge |
137 | STC_AV1 | STC_AV1_INTERRUPT_TIMER0 | Edge |
138 | STC_AV1 | STC_AV1_INTERRUPT_TIMER1 | Edge |
139 | STC_AV1 | STC_AV1_INTERRUPT_TIMER2B | Edge |
140 | STC_AV1 | STC_AV1_INTERRUPT_TIMER3B | Edge |
141 | RTC | SYS_RTC_INT | Edge |
142 | STC_AV2 | STC_AV2_INTERRUPT_TIMER0 | Edge |
143 | STC_AV2 | STC_AV2_INTERRUPT_TIMER1 | Edge |
144 | STC_AV2 | STC_AV2_INTERRUPT_TIMER2B | Edge |
145 | STC_AV2 | STC_AV2_INTERRUPT_TIMER3B | Edge |
146 | STC_AV0 | STC_AV0_INTERRUPT_TIMERW | Level |
147 | STC_AV1 | STC_AV1_INTERRUPT_TIMERW | Level |
148 | UPHY0 | UPHY0_INT | Level |
149 | Reserved | UPHY1_INT | Level |
150 | Reserved | UPHY2_INT | Level |
151 | AHB_DMA | AHB_DMA0_CH0_INT | Level |
152 | AHB_DMA | AHB_DMA0_CH1_INT | Level |
153 | AHB_DMA | AHB_DMA0_CH2_INT | Level |
154 | AHB_DMA | AHB_DMA0_CH3_INT | Level |
155 | AHB_DMA | AHB_DMA0_CH4_INT | Level |
156 | AHB_DMA | AHB_DMA0_CH5_INT | Level |
157 | UART | UA2_INT | Level |
158 | UART | UA3_INT | Level |
159 | UART | UA7_INT | Level |
160 | AHB_DMA | AHB_DMA0_CH6_INT | Level |
161 | AHB_DMA | AHB_DMA0_CH7_INT | Level |
162 | UART | UA6_INT | Level |
163 | Key_Scan | SAR_INT | Level |
164 | Touch_Panel | RES_TOUCH_INT | Edge |
165 | NPU | NPU_XAQ2_INTR | Level |
166 | Reserved | VCDL2_INT | Level |
167 | VC8000D | VCD_INT | Level |
168 | Reserved | VCDDECE_INT | Level |
169 | I2C9 | I2C9_INT | Level |
170 | VI5_CSIIW0 | VI5_CSIIW0_INT_FIELD_START | Level |
171 | VI5_CSIIW0 | VI5_CSIIW0_INT_FIELD_END | Level |
172 | VI5_CSIIW1 | VI5_CSIIW1_INT_FIELD_START | Level |
173 | VI5_CSIIW1 | VI5_CSIIW1_INT_FIELD_END | Level |
174 | VI5_CSIIW2 | VI5_CSIIW2_INT_FIELD_START | Level |
175 | VI5_CSIIW2 | VI5_CSIIW2_INT_FIELD_END | Level |
176 | VI5_CSIIW3 | VI5_CSIIW3_INT_FIELD_START | Level |
177 | VI5_CSIIW3 | VI5_CSIIW3_INT_FIELD_END | Level |
178 | AHB_DMA | AHB_DMA1_CH0_INT | Level |
179 | USB30C0 | USB30C0_INT | Level |
180 | AHB_DMA | AHB_DMA1_CH1_INT | Level |
181 | USBC0 | USBC0_OTG_INT | Level |
182 | USBC0 | USBC0_DEVICE_INT | Level |
183 | USBC0 | USBC0_EHCI_INT | Level |
184 | USBC0 | USBC0_OHCI_INT | Level |
185 | STC_AV4 | STC_AV4_INTERRUPT_TIMERW | Level |
186 | STC_AV4 | STC_AV4_INTERRUPT_TIMER0 | Edge |
187 | STC_AV4 | STC_AV4_INTERRUPT_TIMER1 | Edge |
188 | STC_AV4 | STC_AV4_INTERRUPT_TIMER2B | Edge |
189 | STC_AV4 | STC_AV4_INTERRUPT_TIMER3B | Edge |
190 | Reserved | USBH_OHCI_INT | Level |
191 | U3PHY | U3PHY0_INT | Level |
192 | AHB_DMA | AHB_DMA1_CH2_INT | Level |
193 | AHB_DMA | AHB_DMA1_CH3_INT | Level |
194 | AHB_DMA | AHB_DMA1_CH4_INT | Level |
195 | AHB_DMA | AHB_DMA1_CH5_INT | Level |
196 | AHB_DMA | AHB_DMA1_CH6_INT | Level |
197 | DDRPHY | DDRPHY_INT | Level |
198 | uMCTL2 | UMCTL2_INT | Level |
199 | AHB_DMA | AHB_DMA1_CH7_INT | Level |
200 | GPIO_AO | GPIO_AO_0_INT | Programmable |
201 | GPIO_AO | GPIO_AO_1_INT | Programmable |
202 | GPIO_AO | GPIO_AO_2_INT | Programmable |
203 | GPIO_AO | GPIO_AO_3_INT | Programmable |
204 | GPIO_AO | GPIO_AO_4_INT | Programmable |
205 | GPIO_AO | GPIO_AO_5_INT | Programmable |
206 | GPIO_AO | GPIO_AO_6_INT | Programmable |
207 | GPIO_AO | GPIO_AO_7_INT | Programmable |
208 | GPIO_AO | GPIO_AO_8_INT | Programmable |
209 | GPIO_AO | GPIO_AO_9_INT | Programmable |
210 | GPIO_AO | GPIO_AO_10_INT | Programmable |
211 | GPIO_AO | GPIO_AO_11_INT | Programmable |
212 | GPIO_AO | GPIO_AO_12_INT | Programmable |
213 | GPIO_AO | GPIO_AO_13_INT | Programmable |
214 | GPIO_AO | GPIO_AO_14_INT | Programmable |
215 | GPIO_AO | GPIO_AO_15_INT | Programmable |
216 | GPIO_AO | GPIO_AO_16_INT | Programmable |
217 | GPIO_AO | GPIO_AO_17_INT | Programmable |
218 | GPIO_AO | GPIO_AO_18_INT | Programmable |
219 | GPIO_AO | GPIO_AO_19_INT | Programmable |
220 | GPIO_AO | GPIO_AO_20_INT | Programmable |
221 | GPIO_AO | GPIO_AO_21_INT | Programmable |
222 | GPIO_AO | GPIO_AO_22_INT | Programmable |
223 | GPIO_AO | GPIO_AO_23_INT | Programmable |
224 | GPIO_AO | GPIO_AO_24_INT | Programmable |
225 | GPIO_AO | GPIO_AO_25_INT | Programmable |
226 | GPIO_AO | GPIO_AO_26_INT | Programmable |
227 | GPIO_AO | GPIO_AO_27_INT | Programmable |
228 | GPIO_AO | GPIO_AO_28_INT | Programmable |
229 | GPIO_AO | GPIO_AO_29_INT | Programmable |
230 | GPIO_AO | GPIO_AO_30_INT | Programmable |
231 | GPIO_AO | GPIO_AO_31_INT | Programmable |
[239: 232] | Reserved |
|
|
240 | PMC | PMC_CA55_SCUL3_PDENY_IRQ_CM4 | Level |
241 | PMC | PMC_CA55_CORE3_PDENY_IRQ_CM4 | Level |
242 | PMC | PMC_CA55_CORE2_PDENY_IRQ_CM4 | Level |
243 | PMC | PMC_CA55_CORE1_PDENY_IRQ_CM4 | Level |
244 | PMC | PMC_CA55_CORE0_PDENY_IRQ_CM4 | Level |
245 | PMC | PMC_CA55_SCUL3_PACCEPT_IRQ_CM4 | Level |
246 | PMC | PMC_CA55_CORE3_PACCEPT_IRQ_CM4 | Level |
247 | PMC | PMC_CA55_CORE2_PACCEPT_IRQ_CM4 | Level |
248 | PMC | PMC_CA55_CORE1_PACCEPT_IRQ_CM4 | Level |
249 | PMC | PMC_CA55_CORE0_PACCEPT_IRQ_CM4 | Level |
250 | PMC | PMC_CA55_SCUL3_PACTIVE_ON2OFF_IRQ_CM4 | Level |
251 | PMC | PMC_CA55_CORE3_PACTIVE_ON2OFF_IRQ_CM4 | Level |
252 | PMC | PMC_CA55_CORE2_PACTIVE_ON2OFF_IRQ_CM4 | Level |
253 | PMC | PMC_CA55_CORE1_PACTIVE_ON2OFF_IRQ_CM4 | Level |
254 | PMC | PMC_CA55_CORE0_PACTIVE_ON2OFF_IRQ_CM4 | Level |
255 | PMC | PMC_CA55_SCUL3_PACTIVE_OFF2ON_IRQ_CM4 | Level |
256 | PMC | PMC_CA55_CORE3_PACTIVE_OFF2ON_IRQ_CM4 | Level |
257 | PMC | PMC_CA55_CORE2_PACTIVE_OFF2ON_IRQ_CM4 | Level |
258 | PMC | PMC_CA55_CORE1_PACTIVE_OFF2ON_IRQ_CM4 | Level |
259 | PMC | PMC_CA55_CORE0_PACTIVE_OFF2ON_IRQ_CM4 | Level |
[347307: 260] | Reserved |
| Level |
[415: 308] | CPIOR |
| Level |
[455: 348416] | CPIORReserved |
| Level |
CM4 Interrupt Table
...