本实验以Plus1 7021实践平台配套的FPGA子板和扩展测试子板完成相关实验，FPGA子板的开发工具采用XILINX的Vivado集成开发环境(版本号为2018.3);为了方便将用户自己需要验证的IP方便连接到SOC系统中验证，本实验提供了相应的基础文件，如下
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This experiment uses the FPGA daughter board and extended test daughter board supporting the Plus1 7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses the XILINX Vivado integrated development environment (version number 2018.3); in order to facilitate the user to verify the IP It is convenient to connect to the SOC system for verification. This experiment provides the corresponding basic files, as follows
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5.6.1 Vivado
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software installation
请用户自行安装Xilinx Please install Xilinx Vivado 2018.3以上版本；本实验使用Vivado 2018.3版本,安装完成后桌面出现如下图标3 or above by yourself; this experiment uses Vivado 2018.3 version. After installation, the following icon appears on the desktop
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5.6.2
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FPGA experiment project loading
Double-click the Vivado icon to start running, the following interface appears:
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点击红框Open Click the red box Open Project, 选择ledselect led.xpr under led_7segment_ctl/led目录下的led.xpr,出现如下界面led directory, the following interface appears
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完成项目的加载过程，如下Complete the loading process of the project, as follows
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上图红框的Preject Manager 实现项目的设置，包含源码的添加及修改等The Project Manager in the red box above implements the project settings, including the addition and modification of source code, etc.
5.6.3 FPGA
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本实验所用FPGA子板的输入时钟有两路：
一路是FPGA板上自带的25M时钟GCLK, 在fpga_top.xdc约束文件里有相关约束：
experiment project clock setting
There are two input clocks for the FPGA daughter board used in this experiment: All the way is the 25M clock GCLK that comes with the FPGA board. There are relevant constraints in the soc_top.xdc constraint file: create_clock -period 40.000 -name GCLK -waveform {0.000 20.000} [get_ports GCLK]
接入FPGA后利用其内部自带的PLL IP, 产生项目所需的FBIO TX时钟io_clk，参考时钟ref_clk及系统时钟sysclk；对应的源码文件架构如下
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另一路是FBIO BUS接入FPGA的FBIO RX 36M时钟；在fpga_top.xdc约束文件里有相关约束： After accessing FPGA, use its internal PLL IP to generate the Bus Bridge TX clock io_clk, reference clock ref_clk and system clock sysclk required by the project; the corresponding source file structure is as follows
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The other way is the RX 36M clock of the Bus Bridge connected to the FPGA; there are related constraints in the soc_top.xdc constraint file:
create_clock -period 27.000 -name rclk -waveform {0.000 12.500} [get_ports {FPGA_PAD [35]}] 下面介绍GCLK接入FPGA后利用其内部自带的PLL IP, 产生项目所需的时钟, 参考下图，双击红框，启动PLL 设置操作 The following introduces the use of its internal PLL IP after GCLK is connected to the FPGA to generate the clock required by the project. Refer to the figure below, double-click the red box to start the PLL setting operation
5.6.3.1
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Input clock settings
As shown in the figure below, the PLL input clock comes from the 25M clock on the FPGA daughter board
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5.6.3.2
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PLL输出项目所需的三个时钟，介绍如下：
Output clock setting
The three clocks required for the PLL output project are described as follows: clk_out1 / clk_out2 为FBIO 模组所需，其中本实验中clk_out1为36M,用户可通过修改的设置来改变FBIO TX/RX的传输速度；clk_out3 为FPGA 子板运行的系统时钟65M；is required for the Bus Bridge module. In this experiment, clk_out1 is 36M. The user can change the transmission speed of Bus Bridge TX / RX by modifying the settings; clk_out3 is the system clock 65M running on the FPGA daughter board;
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5.6.4 Reset settings of FPGA
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experiment project
Through Bus Bridge, connect the reset signal generated from SP7021 CPU to FPGA FPGA_PAD [18];
aim_reset_sync.v 模块进行同步化处理后产生FPGA系统所需的复位信号sysrstn，对应的源码文件架构如下
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and performs synchronization processing to generate the reset signal sysrstn required by the FPGA system. The corresponding source file structure is as follows
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5.6.5
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为使设计的时序满足要求，需要对设计进行时序相关的约束，对应的源码文件架构如下
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分析fpga_top.xdc如下：
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Constraint file setting for FPGA experiment project
In order to make the timing of the design meet the requirements, it is necessary to carry out timing-related constraints on the design. The corresponding source file structure is as follows
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Analysis of soc_top.xdc is as follows:
FPGA input clock input constraints
#FPGA clock input
create_clock -period 40.000 -name GCLK -waveform {0.000 20.000} [get_ports GCLK]
create_clock -period 27.000 -name rclk -waveform {0.000 12.500} [get_ports {FPGA_PAD[35]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_apb_bus_m32_bridge_0/FPGA_PAD_IOBUFIBUF[35]_inst/O]
FPGA 系统管脚分配system pin assignment
#FPGA_PADs connection for system
set_property PACKAGE_PIN P17 [get_ports GCLK]
set_property PACKAGE_PIN T8 [get_ports {FPGA_PAD[0]}]
set_property PACKAGE_PIN V9 [get_ports {FPGA_PAD[1]}]
set_property PACKAGE_PIN N6 [get_ports {FPGA_PAD[2]}]
set_property PACKAGE_PIN U6 [get_ports {FPGA_PAD[3]}]
set_property PACKAGE_PIN V6 [get_ports {FPGA_PAD[4]}]
set_property PACKAGE_PIN T6 [get_ports {FPGA_PAD[5]}]
set_property PACKAGE_PIN V4 [get_ports {FPGA_PAD[6]}]
set_property PACKAGE_PIN R6 [get_ports {FPGA_PAD[7]}]
set_property PACKAGE_PIN U4 [get_ports {FPGA_PAD[8]}]
set_property PACKAGE_PIN V2 [get_ports {FPGA_PAD[9]}]
set_property PACKAGE_PIN V1 [get_ports {FPGA_PAD[10]}]
set_property PACKAGE_PIN N5 [get_ports {FPGA_PAD[11]}]
set_property PACKAGE_PIN T5 [get_ports {FPGA_PAD[12]}]
set_property PACKAGE_PIN T3 [get_ports {FPGA_PAD[13]}]
set_property PACKAGE_PIN N4 [get_ports {FPGA_PAD[14]}]
set_property PACKAGE_PIN T1 [get_ports {FPGA_PAD[15]}]
set_property PACKAGE_PIN R2 [get_ports {FPGA_PAD[16]}]
set_property PACKAGE_PIN N1 [get_ports {FPGA_PAD[17]}]
set_property PACKAGE_PIN M1 [get_ports {FPGA_PAD[18]}]
set_property PACKAGE_PIN M3 [get_ports {FPGA_PAD[19]}]
set_property PACKAGE_PIN M2 [get_ports {FPGA_PAD[20]}]
set_property PACKAGE_PIN D8 [get_ports {FPGA_PAD[21]}]
set_property PACKAGE_PIN C7 [get_ports {FPGA_PAD[22]}]
set_property PACKAGE_PIN L1 [get_ports {FPGA_PAD[23]}]
set_property PACKAGE_PIN N2 [get_ports {FPGA_PAD[24]}]
set_property PACKAGE_PIN P2 [get_ports {FPGA_PAD[25]}]
set_property PACKAGE_PIN R1 [get_ports {FPGA_PAD[26]}]
set_property PACKAGE_PIN M4 [get_ports {FPGA_PAD[27]}]
set_property PACKAGE_PIN P3 [get_ports {FPGA_PAD[28]}]
set_property PACKAGE_PIN P4 [get_ports {FPGA_PAD[29]}]
set_property PACKAGE_PIN R3 [get_ports {FPGA_PAD[30]}]
set_property PACKAGE_PIN T4 [get_ports {FPGA_PAD[31]}]
set_property PACKAGE_PIN P5 [get_ports {FPGA_PAD[32]}]
set_property PACKAGE_PIN U1 [get_ports {FPGA_PAD[33]}]
set_property PACKAGE_PIN U2 [get_ports {FPGA_PAD[34]}]
set_property PACKAGE_PIN U3 [get_ports {FPGA_PAD[35]}]
set_property PACKAGE_PIN R5 [get_ports {FPGA_PAD[36]}]
set_property PACKAGE_PIN V5 [get_ports {FPGA_PAD[37]}]
set_property PACKAGE_PIN R7 [get_ports {FPGA_PAD[38]}]
set_property PACKAGE_PIN V7 [get_ports {FPGA_PAD[39]}]
set_property PACKAGE_PIN U7 [get_ports {FPGA_PAD[40]}]
set_property PACKAGE_PIN M6 [get_ports {FPGA_PAD[41]}]
set_property PACKAGE_PIN U9 [get_ports {FPGA_PAD[42]}]
set_property PACKAGE_PIN R8 [get_ports {FPGA_PAD[43]}]
set_property IOSTANDARD LVCMOS33 [get_ports FPGA_PAD*]
set_property IOSTANDARD LVCMOS33 [get_ports GCLK]
set_property PULLDOWN true [get_ports {FPGA_PAD[18]}]
set_property SLEW FAST [get_ports FPGA_PAD*]
FPGA 项目时序例外的约束project timing exception constraints
#Timing exception set
set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *clk_out1*]
set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *clk_out3*]
set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *clk_out2*]
set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *clk_out3*]
set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *clk_out2*]
set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *clk_out1*]
set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *rclk*]
set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out2*]
set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *rclk*]
set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out3*]
set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out1*]
set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *rclk*]
set_false_path -from [get_ports *FPGA_PAD[18]*] -to [all_registers]
set_false_path -from [all_registers] -to [get_ports *FPGA_PAD[19]*]
set_false_path -from [all_registers] -to [get_ports *FPGA_PAD[23]*]
set_max_delay -from [all_registers -edge_triggered] -through [get_nets *FPGA_PAD*] -to [all_outputs] 6.000
set_max_delay -from [all_inputs] -through [get_nets *FPGA_PAD*] -to [all_registers -edge_triggered] 4.000
FPGA 用户IP管脚分配user IP pin assignment
#FPGA_LEDs connection for user IP
set_property PACKAGE_PIN B6 [get_ports {FPGA_LED[0]}]
set_property PACKAGE_PIN A5 [get_ports {FPGA_LED[1]}]
set_property PACKAGE_PIN C5 [get_ports {FPGA_LED[2]}]
set_property PACKAGE_PIN B4 [get_ports {FPGA_LED[3]}]
set_property PACKAGE_PIN B7 [get_ports {FPGA_LED[4]}]
set_property PACKAGE_PIN A6 [get_ports {FPGA_LED[5]}]
set_property PACKAGE_PIN C6 [get_ports {FPGA_LED[6]}]
set_property PACKAGE_PIN C4 [get_ports {FPGA_LED[7]}]
set_property PACKAGE_PIN A3 [get_ports {FPGA_LED[8]}]
set_property PACKAGE_PIN A4 [get_ports {FPGA_LED[9]}]
set_property PACKAGE_PIN D4 [get_ports {FPGA_LED[10]}]
set_property PACKAGE_PIN D5 [get_ports {FPGA_LED[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports FPGA_LED*]
FPGA 编程相关配置，用户不需要修改Note:FPGA programing related configure information，do not modify
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
5.6.6
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Implementation of FPGA experiment project
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上图的3个红框依次运行，完成项目的综合，布局布线的实现以及烧录文件的生成
The three red boxes in the above figure run in sequence to complete the synthesis of the project, the implementation of layout and wiring, and the generation of the burning file
5.6.7
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项目烧录文件生成后，需要下载到FPGA子板上测试，为此需要准备号下载工具与开发板的连接；下图将Xilinx通用的JTAG下载器按图信号连接到fpga子板
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接下来开始FPGA 代码的下载，下面分两种下载方式说明，如下图
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首先按左图红框所示顺序启动下载，得到右图所示Hardware 界面
1) FPGA 代码到下载到内部的SRAM
可实现在线运行及调试，掉电后需要重新下载
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点击红框Program Device下载FPGA 代码到SRAM
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点击红框Program Device完成下载
2) FPGA 代码到下载到外部的Flash
当用户的FPGA代码调试完毕需要固化到板上的Flash时，进行如下操作
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点击红框Add Configuration Memory Device 开始固化FPGA 代码到板上Flash，如下：
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点击OK,出现如下配置文件加载
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FPGA experiment project download
After the project burning file is generated, it needs to be downloaded to the FPGA daughter board for testing. To this end, you need to prepare the connection between the download tool and the development board; the following figure connects the Xilinx universal JTAG downloader to the fpga daughter board according to the figure
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Next, download the FPGA code. There are two download methods, as shown below
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First, start the download in the order shown in the red box on the left to get the Hardware interface shown on the right
1) FPGA code to download to internal SRAM
Can realize online operation and debugging, need to download again after power off
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Click on the red box Program Device to download the FPGA code to SRAM
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Click the red box Program Device to complete the download
2) Download FPGA code to external Flash
When the user's FPGA code is debugged and needs to be solidified to the flash on the board, proceed as follows
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Click the red box Add Configuration Memory Device to start curing the FPGA code to the on-board Flash, as follows:
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Click OK, the following configuration file appears
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Click OK to start programming the SPI Flash configuration
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