Under construction
Software Operation
Software includes I-Boot, X-BootThis article provides a brief overview of the SP7350 software. Subsequent articles will delve into the detailed components of the software. The initial section begins with an introduction to source code and software operations, followed by an explanation of CPU addressing space. The final section touches on the device address map.
Table of Contents
| Table of Contents |
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Source Code
The source code for SP7350 is readily available on both GitHub and Gitee repositories:
GitHub: SP7350 Source Code
Gitee: SP7350 Source Code
For downloading and compiling the code, detailed instructions can be found at:
https://sunplus.atlassian.net/wiki/x/1gB-dg
Additionally, for in-system programming of flash devices on the SP7350 platform, refer to:
https://sunplus.atlassian.net/wiki/x/b4Djdg
Software Operations
The software components include i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux, and FreeRTOS. I-Boot (internal boot) is stored in the IC's internal mask ROM. The operation flow of these components is illustrated in the figure below:
...
Upon power-on reset, when the system initializes, the program counters of all CPUs (four ARM Cortex A55) are set to point to the entry point address of the i-boot program. Once the power-on reset deasserts, the CPUs start executing from the entry point address of the i-boot program. i-boot first initializes the CPU, sets up all interrupt vectors, initializes the stack, initializes the cache, configures serial ports, sets timers, and more. After initialization, it loads x-boot from external storage devices into SRAM and executes it.
X-Boot (external boot) is a first-stage bootloader placed in eMMC, NAND flash, or SD cards, loaded into system SRAM by i-boot. As it runs on SRAM, its size (including code, data, and stack) must not exceed the system SRAM's capacity. The primary task of x-boot is to initialize the DRAM controller and PHY, perform calibration on DRAM PHY and signals, and once calibrated, the DRAM is ready for use. x-boot then switches the CPU from 32-bit mode to 64-bit mode and loads TF-A and U-Boot from external storage into DRAM, executing TF-A.
TF-A (ARM Trusted Firmware-A), developed by ARM, operates at the highest privilege level (EL-3) under ARMv8-A, providing APIs for switching between the secure world and non-secure world. After TF-A completes initialization, it jumps to execute U-Boot (already loaded into DRAM by x-boot).
OP-TEE (Open Portable Trusted Execution Environment)
U-Boot (Universal Boot Loader), developed by Denx Software Engineering, serves as the second-stage bootloader in this system. U-Boot is widely used in embedded systems, supporting various computer architectures. It is free software under the GNU General Public License. As it runs in DRAM, its size is no longer limited by SRAM (only limited by the system's DRAM size), ranging from hundreds of kilobytes to several megabytes. Apart from being a bootloader for the Linux kernel, U-Boot supports access to storage devices like USB flash drives, SD cards, hard disks, reads and burns NOR flash, NAND flash, and eMMC, and supports file systems such as FAT, ext2, ext3, ext4, nfs, ubifs. It also supports network protocols and functions like Ethernet, DHCP, BOOTP, TFTP, NFS, among many others. After initializing itself and external devices, U-Boot then loads Linux from external storage into DRAM and executes it.
Linux is an open-source Unix-like operating system. Linus Torvalds first released its kernel on October 5, 1991. Combined with other utilities, Linux has become a complete operating system. It supports various computer architectures, and anyone can freely use, modify, and redistribute it as long as they adhere to the GNU General Public License. Linux manages all devices on the system, including the CPU, interrupt controller, timer, and DRAM, while all applications run under its management.
FreeRTOS
The following figure illustrates the operation flow of I-Boot, X-Boot, TF-A, OP-TEE, U-Boot, Linux and I-Boot loads X-Boot from external storage device into SRAM and executes it. X-Boot then loads images of TF-A, OP-TEE and U-Boot from external storage device into DRAM and executes TF-A. TF-A runs OP-TEE and then U-Boot, which has already been loaded into DRAM by it. Finally, U-Boot loads Linux from external storage device into DRAM and executes it.
...
...
i-boot loads the x-boot image from an external storage device into SRAM, verifies it, and executes it. x-boot initiates the DDR controller and conducts training for the DDR PHY. Upon the successful completion of DDR PHY training, DDR DRAM becomes operational. Subsequently, x-boot loads TF-A, OP-TEE, and U-Boot images from an external storage device into DRAM, verifying their integrity. Following this, it executes TF-A, which in turn calls OP-TEE and initiates U-Boot. U-Boot loads the Linux image from an external storage device into DRAM and executes it. Once Linux boots successfully, it proceeds to load the firmware of CM4 (FreeRTOS) and starts CM4.
Note that i-boot resides in the chip's internal mask ROM and is a hardware component. x-boot and U-Boot exist temporarily during boot time. Ubuntu server and ROS/ROS2 are optional. After a successful system boot, the stacked software components resemble the figure below:
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CPU (Cortex A55) Addressing Space
The CPU of SP7350 supports a 16 GiB addressing space (with 34 address lines), including 8 GiB for DRAM and 4 GiB reserved for CPIO. The addressing space layout is depicted in three figures for 2 GiB DRAM, 4 GiB DRAM, and 8 GiB DRAM.
Addressing Space for 2 GB DRAM
In the first 4 GiB address space, the initial 2 GiB is allocated for DRAM, while the remaining 0.25 GiB is reserved for chip internal devices and registers. The second and fourth 4 GiB address spaces are reserved, and the third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus.
...
Addressing Space for 4 GB DRAM
The first 0.75 GiB address space is allocated for DRAM, followed by 0.25 GiB for chip internal devices and registers. The initial 0.25 GiB of the second 4 GiB address space is allocated for DRAM, while the remaining 3.75 GiB is reserved. The third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus, and the last 4 GiB address space is reserved.
...
Addressing Space for 8 GB DRAM
The first 4 GiB address space is the same as the layout of 4 GiB DRAM. The second 4 GiB address space is allocated for DRAM, and the third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus. The initial 0.25 GiB of the last 4 GiB address space is allocated for DRAM, while the remaining 3.75 GiB is reserved.
...
Address Map of Devices and Registers
The detailed address map begins at address 0xf0000000. It includes segments such as 64 MiB of SPI-NOR flash, 64 MiB of SPI-NAND flash, device registers, AO device registers, DDR SRAM controller registers, Cortex-A55 registers, Cortex-M4 registers, CBDMA SRAM, CM4 SRAM, 8-bit NAND flash controller, and ROM.
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Interrupt
CA55 Interrupt Table
Bit | Descriptions | Hardware Name | Level/Edge |
0 | Interrupt_from_GPIO | PI_GPIO_INT0 | Programmable |
1 | Interrupt_from_GPIO | PI_GPIO_INT1 | Programmable |
2 | Interrupt_from_GPIO | PI_GPIO_INT2 | Programmable |
3 | Interrupt_from_GPIO | PI_GPIO_INT3 | Programmable |
4 | Interrupt_from_GPIO | PI_GPIO_INT4 | Programmable |
5 | Interrupt_from_GPIO | PI_GPIO_INT5 | Programmable |
6 | Interrupt_from_GPIO | PI_GPIO_INT6 | Programmable |
7 | Interrupt_from_GPIO | PI_GPIO_INT7 | Programmable |
8 | I2C0 | I2C0_INT | Level |
9 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT0 | Level |
10 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT1 | Level |
11 | RTC_2Hz_INT_to_CM4 | RTC_2HZ_INT | Edge |
12 | CPIOR | CPIOR_CTL_INT | Level |
13 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT2 | Level |
14 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT3 | Level |
15 | SDIO_controller | CARD_CTL2_INT | Level |
16 | SD_controller | CARD_CTL1_INT | Level |
17 | EMMC_controller | CARD_CTL0_INT | Level |
18 | SPI_FLASH | SPI_INT | Level |
19 | GMAC | GMAC_INT | Level |
20 | AXI_DMA | AXI_DMA_INT | Level |
21 | GMAC | GMAC_PMT_INT | Level |
22 | I2C6 | I2C6_INT | Level |
23 | SPI_NAND | SPI_ND_INT | Level |
24 | BCH | BCH_INT | Level |
25 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT4 | Level |
26 | MAILBOX0_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT5 | Level |
27 | SPI_CB0 | SPI_CB0_INT | level |
28 | SPI_CB1 | SPI_CB1_INT | level |
29 | SPI_CB2 | SPI_CB2_INT | level |
30 | SPI_CB3 | SPI_CB3_INT | level |
31 | SPI_CB4 | SPI_CB4_INT | level |
32 | SPI_CB5 | SPI_CB5_INT | level |
33 | THERMAL | THERMAL_S_INT | Level |
34 | THERMAL | THERMAL_A_INT | Level |
35 | UART2AXI | UADBG_INT | Level |
36 | VI0_CSIIW0 | VI0_CSIIW0_INT_FIELD_START | Level |
37 | VI0_CSIIW0 | VI0_CSIIW0_INT_FIELD_END | Level |
38 | VI0_CSIIW1 | VI0_CSIIW1_INT_FIELD_START | Level |
39 | VI0_CSIIW1 | VI0_CSIIW1_INT_FIELD_END | Level |
40 | VI1_CSIIW0 | VI1_CSIIW0_INT_FIELD_START | Level |
41 | VI1_CSIIW0 | VI1_CSIIW0_INT_FIELD_END | Level |
42 | VI1_CSIIW1 | VI1_CSIIW1_INT_FIELD_START | Level |
43 | VI1_CSIIW1 | VI1_CSIIW1_INT_FIELD_END | Level |
44 | VI4_CSIIW0 | VI4_CSIIW0_INT_FIELD_START | Level |
45 | VI4_CSIIW0 | VI4_CSIIW0_INT_FIELD_END | Level |
46 | VI4_CSIIW1 | VI4_CSIIW1_INT_FIELD_START | Level |
47 | VI4_CSIIW1 | VI4_CSIIW1_INT_FIELD_END | Level |
48 | SEC_IP | SEC_INT | Level |
49 | AXI_Global_Monitor_int | AXI_MON_TOP_INT | Level |
50 | AXI_Global_Monitor_int | AXI_MON_PAI_INT | Level |
51 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMERW | Level |
52 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER0 | Edge |
53 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER1 | Edge |
54 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER2B | Edge |
55 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER3B | Edge |
56 | RTC | WakeupKey_INT | Level |
57 | TZC400 | TZC_400_INT | Level |
58 | GMAC | GMAC_LPI_INT | Level |
59 | MIPITX | MIPITX_INT | Level |
60 | UART | UA0_INT | Level |
61 | UART | UA1_INT | Level |
62 | Reserved | AXI_MON_TOP_INT | Level |
63 | DISP_PWM | DISP_PWM_USER_INT_0 | Edge |
64 | DISP_PWM | DISP_PWM_INT_END_0 | Edge |
65 | DISP_PWM | DISP_PWM_USER_INT_1 | Edge |
66 | DISP_PWM | DISP_PWM_INT_END_1 | Edge |
67 | DISP_PWM | DISP_PWM_USER_INT_2 | Edge |
68 | DISP_PWM | DISP_PWM_INT_END_2 | Edge |
69 | DISP_PWM | DISP_PWM_USER_INT_3 | Edge |
70 | DISP_PWM | DISP_PWM_INT_END_3 | Edge |
71 | PNAND | PNAND_INT | level |
72 | RBUS_in_AO | RBUS_INTERRUPT | Level |
73 | Reserved | AXI_MON_PAI_INT | Level |
74 | CB_DMA0 | CBDMA0_INT | Level |
75 | Reserved | AXI_MON_PAII_INT | Level |
76 | RBUS | RBUS_INTERRUPT | Level |
77 | VC8000E | VCE_INT | Level |
78 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT6 | Level |
79 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT7 | Level |
80 | VI23_CSIIW0 | VI23_CSIIW0_INT_FIELD_START | Level |
81 | VI23_CSIIW0 | VI23_CSIIW0_INT_FIELD_END | Level |
82 | VI23_CSIIW1 | VI23_CSIIW1_INT_FIELD_START | Level |
83 | VI23_CSIIW1 | VI23_CSIIW1_INT_FIELD_END | Level |
84 | VI23_CSIIW2 | VI23_CSIIW2_INT_FIELD_START | Level |
85 | VI23_CSIIW2 | VI23_CSIIW2_INT_FIELD_END | Level |
86 | VI23_CSIIW3 | VI23_CSIIW3_INT_FIELD_START | Level |
87 | VI23_CSIIW3 | VI23_CSIIW3_INT_FIELD_END | Level |
88 | VCL | VCL_INTR0 | Level |
89 | VCL | VCL_INTR1 | Level |
90 | VCL | VCL_INTR2 | Level |
91 | VCL | VCL_INTR3 | Level |
92 | VCL | VCL_INTR4 | Level |
93 | VCL | VCL_INTR5 | Level |
94 | I2C1 | I2C1_INT | Level |
95 | I2C2 | I2C2_INT | Level |
96 | I2C3 | I2C3_INT | Level |
97 | I2C4 | I2C4_INT | Level |
98 | I2C5 | I2C5_INT | Level |
99 | RTC | RTC_PERIODIC_INT | Edge |
100 | AUD | LOSD_INT | Edge |
101 | AUD | AUD_FIFO_INT | Level |
102 | AUD | AUD_TWS_LATCH_INT | Level |
103 | AUD | AUD_TWS_SAMPLE_INT | Level |
104 | TGEN | TGEN_INT_FIELD_START | Edge |
105 | TGEN | TGEN_INT_FIELD_END | Edge |
106 | TGEN | TGEN_INT_USER1 | Edge |
107 | TGEN | TGEN_INT_USER2 | Edge |
108 | VCL | VCL_INTR6 | Edge |
109 | VCL | VCL_INTR7 | Level |
110 | I2C7 | I2C7_INT | Level |
111 | I2C8 | I2C8_INT | Level |
112 | PNAND | PNAND_ERROR_INT | level |
113 | STC_AV3 | STC_AV3_INTERRUPT_TIMERW | Level |
114 | STC_AV3 | STC_AV3_INTERRUPT_TIMER0 | Edge |
115 | STC_AV3 | STC_AV3_INTERRUPT_TIMER1 | Edge |
116 | STC_AV3 | STC_AV3_INTERRUPT_TIMER2B | Edge |
117 | STC_AV3 | STC_AV3_INTERRUPT_TIMER3B | Edge |
118 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT0 | Level |
119 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT1 | Level |
120 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT2 | Level |
121 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT3 | Level |
122 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT4 | Level |
123 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT5 | Level |
124 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT6 | Level |
125 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT7 | Level |
126 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_INT | Level |
127 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_INT | Level |
128 | STC | STC_INTERRUPT_TIMERW | Level |
129 | STC | STC_INTERRUPT_TIMER0 | Edge |
130 | STC | STC_INTERRUPT_TIMER1 | Edge |
131 | STC | STC_INTERRUPT_TIMER2B | Edge |
132 | STC | STC_INTERRUPT_TIMER3B | Edge |
133 | STC_AV0 | STC_AV0_INTERRUPT_TIMER0 | Edge |
134 | STC_AV0 | STC_AV0_INTERRUPT_TIMER1 | Edge |
135 | STC_AV0 | STC_AV0_INTERRUPT_TIMER2B | Edge |
136 | STC_AV0 | STC_AV0_INTERRUPT_TIMER3B | Edge |
137 | STC_AV1 | STC_AV1_INTERRUPT_TIMER0 | Edge |
138 | STC_AV1 | STC_AV1_INTERRUPT_TIMER1 | Edge |
139 | STC_AV1 | STC_AV1_INTERRUPT_TIMER2B | Edge |
140 | STC_AV1 | STC_AV1_INTERRUPT_TIMER3B | Edge |
141 | RTC | SYS_RTC_INT | Edge |
142 | STC_AV2 | STC_AV2_INTERRUPT_TIMER0 | Edge |
143 | STC_AV2 | STC_AV2_INTERRUPT_TIMER1 | Edge |
144 | STC_AV2 | STC_AV2_INTERRUPT_TIMER2B | Edge |
145 | STC_AV2 | STC_AV2_INTERRUPT_TIMER3B | Edge |
146 | STC_AV0 | STC_AV0_INTERRUPT_TIMERW | Level |
147 | STC_AV1 | STC_AV1_INTERRUPT_TIMERW | Level |
148 | UPHY0 | UPHY0_INT | Level |
149 | Reserved | UPHY1_INT | Level |
150 | Reserved | UPHY2_INT | Level |
151 | AHB_DMA | AHB_DMA0_CH0_INT | Level |
152 | AHB_DMA | AHB_DMA0_CH1_INT | Level |
153 | AHB_DMA | AHB_DMA0_CH2_INT | Level |
154 | AHB_DMA | AHB_DMA0_CH3_INT | Level |
155 | AHB_DMA | AHB_DMA0_CH4_INT | Level |
156 | AHB_DMA | AHB_DMA0_CH5_INT | Level |
157 | UART | UA2_INT | Level |
158 | UART | UA3_INT | Level |
159 | UART | UA7_INT | Level |
160 | AHB_DMA | AHB_DMA0_CH6_INT | Level |
161 | AHB_DMA | AHB_DMA0_CH7_INT | Level |
162 | UART | UA6_INT | Level |
163 | Key_Scan | SAR_INT | Level |
164 | Touch_Panel | RES_TOUCH_INT | Edge |
165 | NPU | NPU_XAQ2_INTR | Level |
166 | Reserved | VCDL2_INT | Level |
167 | VC8000D | VCD_INT | Level |
168 | Reserved | VCDDECE_INT | Level |
169 | I2C9 | I2C9_INT | Level |
170 | VI5_CSIIW0 | VI5_CSIIW0_INT_FIELD_START | Level |
171 | VI5_CSIIW0 | VI5_CSIIW0_INT_FIELD_END | Level |
172 | VI5_CSIIW1 | VI5_CSIIW1_INT_FIELD_START | Level |
173 | VI5_CSIIW1 | VI5_CSIIW1_INT_FIELD_END | Level |
174 | VI5_CSIIW2 | VI5_CSIIW2_INT_FIELD_START | Level |
175 | VI5_CSIIW2 | VI5_CSIIW2_INT_FIELD_END | Level |
176 | VI5_CSIIW3 | VI5_CSIIW3_INT_FIELD_START | Level |
177 | VI5_CSIIW3 | VI5_CSIIW3_INT_FIELD_END | Level |
178 | AHB_DMA | AHB_DMA1_CH0_INT | Level |
179 | USB30C0 | USB30C0_INT | Level |
180 | AHB_DMA | AHB_DMA1_CH1_INT | Level |
181 | USBC0 | USBC0_OTG_INT | Level |
182 | USBC0 | USBC0_DEVICE_INT | Level |
183 | USBC0 | USBC0_EHCI_INT | Level |
184 | USBC0 | USBC0_OHCI_INT | Level |
185 | STC_AV4 | STC_AV4_INTERRUPT_TIMERW | Level |
186 | STC_AV4 | STC_AV4_INTERRUPT_TIMER0 | Edge |
187 | STC_AV4 | STC_AV4_INTERRUPT_TIMER1 | Edge |
188 | STC_AV4 | STC_AV4_INTERRUPT_TIMER2B | Edge |
189 | STC_AV4 | STC_AV4_INTERRUPT_TIMER3B | Edge |
190 | Reserved | USBH_OHCI_INT | Level |
191 | U3PHY | U3PHY0_INT | Level |
192 | AHB_DMA | AHB_DMA1_CH2_INT | Level |
193 | AHB_DMA | AHB_DMA1_CH3_INT | Level |
194 | AHB_DMA | AHB_DMA1_CH4_INT | Level |
195 | AHB_DMA | AHB_DMA1_CH5_INT | Level |
196 | AHB_DMA | AHB_DMA1_CH6_INT | Level |
197 | DDRPHY | DDRPHY_INT | Level |
198 | uMCTL2 | UMCTL2_INT | Level |
199 | AHB_DMA | AHB_DMA1_CH7_INT | Level |
200 | GPIO_AO | GPIO_AO_0_INT | Programmable |
201 | GPIO_AO | GPIO_AO_1_INT | Programmable |
202 | GPIO_AO | GPIO_AO_2_INT | Programmable |
203 | GPIO_AO | GPIO_AO_3_INT | Programmable |
204 | GPIO_AO | GPIO_AO_4_INT | Programmable |
205 | GPIO_AO | GPIO_AO_5_INT | Programmable |
206 | GPIO_AO | GPIO_AO_6_INT | Programmable |
207 | GPIO_AO | GPIO_AO_7_INT | Programmable |
208 | GPIO_AO | GPIO_AO_8_INT | Programmable |
209 | GPIO_AO | GPIO_AO_9_INT | Programmable |
210 | GPIO_AO | GPIO_AO_10_INT | Programmable |
211 | GPIO_AO | GPIO_AO_11_INT | Programmable |
212 | GPIO_AO | GPIO_AO_12_INT | Programmable |
213 | GPIO_AO | GPIO_AO_13_INT | Programmable |
214 | GPIO_AO | GPIO_AO_14_INT | Programmable |
215 | GPIO_AO | GPIO_AO_15_INT | Programmable |
216 | GPIO_AO | GPIO_AO_16_INT | Programmable |
217 | GPIO_AO | GPIO_AO_17_INT | Programmable |
218 | GPIO_AO | GPIO_AO_18_INT | Programmable |
219 | GPIO_AO | GPIO_AO_19_INT | Programmable |
220 | GPIO_AO | GPIO_AO_20_INT | Programmable |
221 | GPIO_AO | GPIO_AO_21_INT | Programmable |
222 | GPIO_AO | GPIO_AO_22_INT | Programmable |
223 | GPIO_AO | GPIO_AO_23_INT | Programmable |
224 | GPIO_AO | GPIO_AO_24_INT | Programmable |
225 | GPIO_AO | GPIO_AO_25_INT | Programmable |
226 | GPIO_AO | GPIO_AO_26_INT | Programmable |
227 | GPIO_AO | GPIO_AO_27_INT | Programmable |
228 | GPIO_AO | GPIO_AO_28_INT | Programmable |
229 | GPIO_AO | GPIO_AO_29_INT | Programmable |
230 | GPIO_AO | GPIO_AO_30_INT | Programmable |
231 | GPIO_AO | GPIO_AO_31_INT | Programmable |
[239: 232] | Reserved |
|
|
240 | PMC | PMC_CA55_SCUL3_PDENY_IRQ_CM4 | Level |
241 | PMC | PMC_CA55_CORE3_PDENY_IRQ_CM4 | Level |
242 | PMC | PMC_CA55_CORE2_PDENY_IRQ_CM4 | Level |
243 | PMC | PMC_CA55_CORE1_PDENY_IRQ_CM4 | Level |
244 | PMC | PMC_CA55_CORE0_PDENY_IRQ_CM4 | Level |
245 | PMC | PMC_CA55_SCUL3_PACCEPT_IRQ_CM4 | Level |
246 | PMC | PMC_CA55_CORE3_PACCEPT_IRQ_CM4 | Level |
247 | PMC | PMC_CA55_CORE2_PACCEPT_IRQ_CM4 | Level |
248 | PMC | PMC_CA55_CORE1_PACCEPT_IRQ_CM4 | Level |
249 | PMC | PMC_CA55_CORE0_PACCEPT_IRQ_CM4 | Level |
250 | PMC | PMC_CA55_SCUL3_PACTIVE_ON2OFF_IRQ_CM4 | Level |
251 | PMC | PMC_CA55_CORE3_PACTIVE_ON2OFF_IRQ_CM4 | Level |
252 | PMC | PMC_CA55_CORE2_PACTIVE_ON2OFF_IRQ_CM4 | Level |
253 | PMC | PMC_CA55_CORE1_PACTIVE_ON2OFF_IRQ_CM4 | Level |
254 | PMC | PMC_CA55_CORE0_PACTIVE_ON2OFF_IRQ_CM4 | Level |
255 | PMC | PMC_CA55_SCUL3_PACTIVE_OFF2ON_IRQ_CM4 | Level |
256 | PMC | PMC_CA55_CORE3_PACTIVE_OFF2ON_IRQ_CM4 | Level |
257 | PMC | PMC_CA55_CORE2_PACTIVE_OFF2ON_IRQ_CM4 | Level |
258 | PMC | PMC_CA55_CORE1_PACTIVE_OFF2ON_IRQ_CM4 | Level |
259 | PMC | PMC_CA55_CORE0_PACTIVE_OFF2ON_IRQ_CM4 | Level |
[307: 260] | Reserved |
| Level |
[415: 308] | CPIOR |
| Level |
[455: 416] | Reserved |
| Level |
CM4 Interrupt Table
Bit | Descriptions | Hardware Name | Level/Edge |
0 | Main_Domain_Power_UP_Req | MAIN_PWR_UP_REQ | level |
1 | Main_Domain_Power_Dwon_Ack | MAIN_PWR_DOWN_INT | level |
2 | RTC | WakeupKey_INT | Level |
3 |
|
|
|
4 |
|
|
|
5 |
|
|
|
6 |
|
|
|
7 |
|
|
|
8 | I2C0 | I2C0_INT | Level |
9 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT0 | Level |
10 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT1 | Level |
11 | RTC_2HZ_INT_to_CM4 | RTC_2HZ_INT | Edge |
12 |
|
|
|
13 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT2 | Level |
14 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT3 | Level |
15 |
|
|
|
16 |
|
|
|
17 |
|
|
|
18 |
|
|
|
19 |
|
|
|
20 |
|
|
|
21 |
|
|
|
22 | I2C6 | I2C6_INT | Level |
23 |
|
|
|
24 |
|
|
|
25 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT4 | Level |
26 | MAILBOX0_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT5 | Level |
27 | SPI_CB0 | SPI_CB0_INT | level |
28 | SPI_CB1 | SPI_CB1_INT | level |
29 | SPI_CB2 | SPI_CB2_INT | level |
30 | SPI_CB3 | SPI_CB3_INT | level |
31 | SPI_CB4 | SPI_CB4_INT | level |
32 | SPI_CB5 | SPI_CB5_INT | level |
33 | THERMAL | THERMAL_S_INT | Level |
34 | THERMAL | THERMAL_A_INT | Level |
35 | Reserved | UADBG_INT | Level |
36 | GPIO_AO | GPIO_AO_0_INT | Programmable |
37 | GPIO_AO | GPIO_AO_1_INT | Programmable |
38 | GPIO_AO | GPIO_AO_2_INT | Programmable |
39 | GPIO_AO | GPIO_AO_3_INT | Programmable |
40 | GPIO_AO | GPIO_AO_4_INT | Programmable |
41 | GPIO_AO | GPIO_AO_5_INT | Programmable |
42 | GPIO_AO | GPIO_AO_6_INT | Programmable |
43 | GPIO_AO | GPIO_AO_7_INT | Programmable |
44 | GPIO_AO | GPIO_AO_8_INT | Programmable |
45 | GPIO_AO | GPIO_AO_9_INT | Programmable |
46 | GPIO_AO | GPIO_AO_10_INT | Programmable |
47 | GPIO_AO | GPIO_AO_11_INT | Programmable |
48 | GPIO_AO | GPIO_AO_12_INT | Programmable |
49 | GPIO_AO | GPIO_AO_13_INT | Programmable |
50 | GPIO_AO | GPIO_AO_14_INT | Programmable |
51 | GPIO_AO | GPIO_AO_15_INT | Programmable |
52 | GPIO_AO | GPIO_AO_16_INT | Programmable |
53 | GPIO_AO | GPIO_AO_17_INT | Programmable |
54 | GPIO_AO | GPIO_AO_18_INT | Programmable |
55 | GPIO_AO | GPIO_AO_19_INT | Programmable |
56 | GPIO_AO | GPIO_AO_20_INT | Programmable |
57 | GPIO_AO | GPIO_AO_21_INT | Programmable |
58 | GPIO_AO | GPIO_AO_22_INT | Programmable |
59 |
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60 | UART | UA0_INT | Level |
61 | UART | UA1_INT | Level |
62 |
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63 | DISP_PWM | DISP_PWM_USER_INT_0 | Edge |
64 | DISP_PWM | DISP_PWM_INT_END_0 | Edge |
65 | DISP_PWM | DISP_PWM_USER_INT_1 | Edge |
66 | DISP_PWM | DISP_PWM_INT_END_1 | Edge |
67 | DISP_PWM | DISP_PWM_USER_INT_2 | Edge |
68 | DISP_PWM | DISP_PWM_INT_END_2 | Edge |
69 | DISP_PWM | DISP_PWM_USER_INT_3 | Edge |
70 | DISP_PWM | DISP_PWM_INT_END_3 | Edge |
71 |
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72 | RBUS_in_AO | RBUS_INTERRUPT | Level |
73 |
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74 |
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75 |
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76 |
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77 |
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78 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT6 | Level |
79 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_DIRECT_INT7 | Level |
80 | GPIO_AO | GPIO_AO_23_INT | Programmable |
81 | GPIO_AO | GPIO_AO_24_INT | Programmable |
82 | GPIO_AO | GPIO_AO_25_INT | Programmable |
83 | GPIO_AO | GPIO_AO_26_INT | Programmable |
84 | GPIO_AO | GPIO_AO_27_INT | Programmable |
85 | GPIO_AO | GPIO_AO_28_INT | Programmable |
86 | GPIO_AO | GPIO_AO_29_INT | Programmable |
87 | GPIO_AO | GPIO_AO_30_INT | Programmable |
88 | GPIO_AO | GPIO_AO_31_INT | Programmable |
89 |
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90 |
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91 |
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92 |
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93 |
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94 | I2C1 | I2C1_INT | Level |
95 | I2C2 | I2C2_INT | Level |
96 | I2C3 | I2C3_INT | Level |
97 | I2C4 | I2C4_INT | Level |
98 | I2C5 | I2C5_INT | Level |
99 | RTC | RTC_PERIODIC_INT | Edge |
100 | AUD | LOSD_INT | Edge |
101 | AUD | AUD_FIFO_INT | Level |
102 | AUD | AUD_TWS_LATCH_INT | Level |
103 | AUD | AUD_TWS_SAMPLE_INT | Level |
104 |
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105 |
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106 |
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107 |
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108 |
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109 |
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110 | I2C7 | I2C7_INT | Level |
111 | I2C8 | I2C8_INT | Level |
112 | I2C9 | I2C9_INT | Level |
113 | Reserved | STC_AV3_INTERRUPT_TIMERW | Level |
114 | Reserved | STC_AV3_INTERRUPT_TIMER0 | Edge |
115 | Reserved | STC_AV3_INTERRUPT_TIMER1 | Edge |
116 | Reserved | STC_AV3_INTERRUPT_TIMER2B | Edge |
117 | Reserved | STC_AV3_INTERRUPT_TIMER3B | Edge |
118 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT0 | Level |
119 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT1 | Level |
120 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT2 | Level |
121 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT3 | Level |
122 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT4 | Level |
123 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT5 | Level |
124 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT6 | Level |
125 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_DIRECT_INT7 | Level |
126 | MAILBOX1_CM4_to_CA55 | CPU2_TO_0_INT | Level |
127 | MAILBOX1_CA55_to_CM4 | CPU0_TO_2_INT | Level |
128 | STC | STC_INTERRUPT_TIMERW | Level |
129 | STC | STC_INTERRUPT_TIMER0 | Edge |
130 | STC | STC_INTERRUPT_TIMER1 | Edge |
131 | STC | STC_INTERRUPT_TIMER2B | Edge |
132 | STC | STC_INTERRUPT_TIMER3B | Edge |
133 | STC_AV0 | STC_AV0_INTERRUPT_TIMER0 | Edge |
134 | STC_AV0 | STC_AV0_INTERRUPT_TIMER1 | Edge |
135 | STC_AV0 | STC_AV0_INTERRUPT_TIMER2B | Edge |
136 | STC_AV0 | STC_AV0_INTERRUPT_TIMER3B | Edge |
137 | STC_AV1 | STC_AV1_INTERRUPT_TIMER0 | Edge |
138 | STC_AV1 | STC_AV1_INTERRUPT_TIMER1 | Edge |
139 | STC_AV1 | STC_AV1_INTERRUPT_TIMER2B | Edge |
140 | STC_AV1 | STC_AV1_INTERRUPT_TIMER3B | Edge |
141 | RTC | SYS_RTC_INT | Edge |
142 | STC_AV2 | STC_AV2_INTERRUPT_TIMER0 | Edge |
143 | STC_AV2 | STC_AV2_INTERRUPT_TIMER1 | Edge |
144 | STC_AV2 | STC_AV2_INTERRUPT_TIMER2B | Edge |
145 | STC_AV2 | STC_AV2_INTERRUPT_TIMER3B | Edge |
146 | STC_AV0 | STC_AV0_INTERRUPT_TIMERW | Level |
147 | STC_AV1 | STC_AV1_INTERRUPT_TIMERW | Level |
148 |
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149 |
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150 |
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151 | AHB_DMA | AHB_DMA0_CH0_INT | Level |
152 | AHB_DMA | AHB_DMA0_CH1_INT | Level |
153 | AHB_DMA | AHB_DMA0_CH2_INT | Level |
154 | AHB_DMA | AHB_DMA0_CH3_INT | Level |
155 | AHB_DMA | AHB_DMA0_CH4_INT | Level |
156 | AHB_DMA | AHB_DMA0_CH5_INT | Level |
157 | UART | UA2_INT | Level |
158 | UART | UA3_INT | Level |
159 | UART | UA7_INT | Level |
160 | AHB_DMA | AHB_DMA0_CH6_INT | Level |
161 | AHB_DMA | AHB_DMA0_CH7_INT | Level |
162 | UART | UA6_INT | Level |
163 | Key_Scan | SAR_INT | Level |
164 | Touch_Panel | RES_TOUCH_INT | Edge |
165 | PMC | PMC_CA55_SCUL3_PDENY_IRQ_CM4 | Level |
166 | PMC | PMC_CA55_CORE3_PDENY_IRQ_CM4 | Level |
167 | PMC | PMC_CA55_CORE2_PDENY_IRQ_CM4 | Level |
168 | PMC | PMC_CA55_CORE1_PDENY_IRQ_CM4 | Level |
169 | PMC | PMC_CA55_CORE0_PDENY_IRQ_CM4 | Level |
170 | PMC | PMC_CA55_SCUL3_PACCEPT_IRQ_CM4 | Level |
171 | PMC | PMC_CA55_CORE3_PACCEPT_IRQ_CM4 | Level |
172 | PMC | PMC_CA55_CORE2_PACCEPT_IRQ_CM4 | Level |
173 | PMC | PMC_CA55_CORE1_PACCEPT_IRQ_CM4 | Level |
174 | PMC | PMC_CA55_CORE0_PACCEPT_IRQ_CM4 | Level |
175 |
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176 |
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177 |
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178 | AHB_DMA | AHB_DMA1_CH0_INT | Level |
179 |
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180 | AHB_DMA | AHB_DMA1_CH1_INT | Level |
181 |
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182 |
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183 |
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184 |
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185 | STC_AV4 | STC_AV4_INTERRUPT_TIMERW | Level |
186 | STC_AV4 | STC_AV4_INTERRUPT_TIMER0 | Edge |
187 | STC_AV4 | STC_AV4_INTERRUPT_TIMER1 | Edge |
188 | STC_AV4 | STC_AV4_INTERRUPT_TIMER2B | Edge |
189 | STC_AV4 | STC_AV4_INTERRUPT_TIMER3B | Edge |
190 |
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191 |
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192 | AHB_DMA | AHB_DMA1_CH2_INT | Level |
193 | AHB_DMA | AHB_DMA1_CH3_INT | Level |
194 | AHB_DMA | AHB_DMA1_CH4_INT | Level |
195 | AHB_DMA | AHB_DMA1_CH5_INT | Level |
196 | AHB_DMA | AHB_DMA1_CH6_INT | Level |
197 |
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198 |
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199 | AHB_DMA | AHB_DMA1_CH7_INT | Level |
[200: 229] | CPIO_bypass_intr | INTERRUPT_DEF2AO[49:20] | Level |
230 | PMC | PMC_CA55_SCUL3_PACTIVE_ON2OFF_IRQ_CM4 | Level |
231 | PMC | PMC_CA55_CORE3_PACTIVE_ON2OFF_IRQ_CM4 | Level |
232 | PMC | PMC_CA55_CORE2_PACTIVE_ON2OFF_IRQ_CM4 | Level |
233 | PMC | PMC_CA55_CORE1_PACTIVE_ON2OFF_IRQ_CM4 | Level |
234 | PMC | PMC_CA55_CORE0_PACTIVE_ON2OFF_IRQ_CM4 | Level |
235 | PMC | PMC_CA55_SCUL3_PACTIVE_OFF2ON_IRQ_CM4 | Level |
236 | PMC | PMC_CA55_CORE3_PACTIVE_OFF2ON_IRQ_CM4 | Level |
237 | PMC | PMC_CA55_CORE2_PACTIVE_OFF2ON_IRQ_CM4 | Level |
238 | PMC | PMC_CA55_CORE1_PACTIVE_OFF2ON_IRQ_CM4 | Level |
239 | PMC | PMC_CA55_CORE0_PACTIVE_OFF2ON_IRQ_CM4 | Level |
[200: 229] | CPIO_bypass_intr | INTERRUPT_DEF2AO[49:20] | Level |
230 | PMC | PMC_CA55_SCUL3_PACTIVE_ON2OFF_IRQ_CM4 | Level |
231 | PMC | PMC_CA55_CORE3_PACTIVE_ON2OFF_IRQ_CM4 | Level |
232 | PMC | PMC_CA55_CORE2_PACTIVE_ON2OFF_IRQ_CM4 | Level |
233 | PMC | PMC_CA55_CORE1_PACTIVE_ON2OFF_IRQ_CM4 | Level |
234 | PMC | PMC_CA55_CORE0_PACTIVE_ON2OFF_IRQ_CM4 | Level |
235 | PMC | PMC_CA55_SCUL3_PACTIVE_OFF2ON_IRQ_CM4 | Level |
236 | PMC | PMC_CA55_CORE3_PACTIVE_OFF2ON_IRQ_CM4 | Level |
237 | PMC | PMC_CA55_CORE2_PACTIVE_OFF2ON_IRQ_CM4 | Level |
238 | PMC | PMC_CA55_CORE1_PACTIVE_OFF2ON_IRQ_CM4 | Level |
239 | PMC | PMC_CA55_CORE0_PACTIVE_OFF2ON_IRQ_CM4 | Level |
CPIOR Bypass Interrupt Table
C3V to other P-chip interrupts through CPIO.
Bit | Description | Hardware Name | Level/Edge |
0 | I2C0 | I2C0_INT | Level |
1 | RTC_2Hz_INT_to_CM4 | RTC_2HZ_INT | Edge |
2 | CPIOR | CPIOR_CTL_INT | Level |
3 | SDIO_controller | CARD_CTL2_INT | Level |
4 | SD_controller | CARD_CTL1_INT | Level |
5 | GMAC | GMAC_INT | Level |
6 | AXI_DMA | AXI_DMA_INT | Level |
7 | GMAC | GMAC_PMT_INT | Level |
8 | I2C6 | I2C6_INT | Level |
9 | SPI_CB0 | SPI_CB0_INT | level |
10 | SPI_CB1 | SPI_CB1_INT | level |
11 | SPI_CB2 | SPI_CB2_INT | level |
12 | SPI_CB3 | SPI_CB3_INT | level |
13 | SPI_CB4 | SPI_CB4_INT | level |
14 | SPI_CB5 | SPI_CB5_INT | level |
15 | UART2AXI | UADBG_INT | Level |
16 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMERW | Level |
17 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER0 | Edge |
18 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER1 | Edge |
19 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER2B | Edge |
20 | STC_TIMESTAMP | STC_TIMESTAMP_INTERRUPT_TIMER3B | Edge |
21 | RTC | WakeupKey_INT | Level |
22 | GMAC | GMAC_LPI_INT | Level |
23 | UART | UA0_INT | Level |
24 | UART | UA1_INT | Level |
25 | DISP_PWM | DISP_PWM_USER_INT_0 | Edge |
26 | DISP_PWM | DISP_PWM_INT_END_0 | Edge |
27 | DISP_PWM | DISP_PWM_USER_INT_1 | Edge |
28 | DISP_PWM | DISP_PWM_INT_END_1 | Edge |
29 | DISP_PWM | DISP_PWM_USER_INT_2 | Edge |
30 | DISP_PWM | DISP_PWM_INT_END_2 | Edge |
31 | DISP_PWM | DISP_PWM_USER_INT_3 | Edge |
32 | DISP_PWM | DISP_PWM_INT_END_3 | Edge |
33 | CB_DMA0 | CBDMA0_INT | Level |
34 | I2C1 | I2C1_INT | Level |
35 | I2C2 | I2C2_INT | Level |
36 | I2C3 | I2C3_INT | Level |
37 | I2C4 | I2C4_INT | Level |
38 | I2C5 | I2C5_INT | Level |
39 | RTC | RTC_PERIODIC_INT | Edge |
40 | AUD | LOSD_INT | Edge |
41 | AUD | AUD_FIFO_INT | Level |
42 | AUD | AUD_TWS_LATCH_INT | Level |
43 | AUD | AUD_TWS_SAMPLE_INT | Level |
44 | I2C7 | I2C7_INT | Level |
45 | I2C8 | I2C8_INT | Level |
46 | PNAND | PNAND_ERROR_INT | level |
47 | STC_AV3 | STC_AV3_INTERRUPT_TIMERW | Level |
48 | STC_AV3 | STC_AV3_INTERRUPT_TIMER0 | Edge |
49 | STC_AV3 | STC_AV3_INTERRUPT_TIMER1 | Edge |
50 | STC_AV3 | STC_AV3_INTERRUPT_TIMER2B | Edge |
51 | STC_AV3 | STC_AV3_INTERRUPT_TIMER3B | Edge |
52 | STC | STC_INTERRUPT_TIMERW | Level |
53 | STC | STC_INTERRUPT_TIMER0 | Edge |
54 | STC | STC_INTERRUPT_TIMER1 | Edge |
55 | STC | STC_INTERRUPT_TIMER2B | Edge |
56 | STC | STC_INTERRUPT_TIMER3B | Edge |
57 | STC_AV0 | STC_AV0_INTERRUPT_TIMER0 | Edge |
58 | STC_AV0 | STC_AV0_INTERRUPT_TIMER1 | Edge |
59 | STC_AV0 | STC_AV0_INTERRUPT_TIMER2B | Edge |
60 | STC_AV0 | STC_AV0_INTERRUPT_TIMER3B | Edge |
61 | STC_AV1 | STC_AV1_INTERRUPT_TIMER0 | Edge |
62 | STC_AV1 | STC_AV1_INTERRUPT_TIMER1 | Edge |
63 | STC_AV1 | STC_AV1_INTERRUPT_TIMER2B | Edge |
64 | STC_AV1 | STC_AV1_INTERRUPT_TIMER3B | Edge |
65 | RTC | SYS_RTC_INT | Edge |
66 | STC_AV2 | STC_AV2_INTERRUPT_TIMER0 | Edge |
67 | STC_AV2 | STC_AV2_INTERRUPT_TIMER1 | Edge |
68 | STC_AV2 | STC_AV2_INTERRUPT_TIMER2B | Edge |
69 | STC_AV2 | STC_AV2_INTERRUPT_TIMER3B | Edge |
70 | STC_AV0 | STC_AV0_INTERRUPT_TIMERW | Level |
71 | STC_AV1 | STC_AV1_INTERRUPT_TIMERW | Level |
72 | UPHY0 | UPHY0_INT | Level |
73 | AHB_DMA | AHB_DMA0_CH0_INT | Level |
74 | AHB_DMA | AHB_DMA0_CH1_INT | Level |
75 | AHB_DMA | AHB_DMA0_CH2_INT | Level |
76 | AHB_DMA | AHB_DMA0_CH3_INT | Level |
77 | AHB_DMA | AHB_DMA0_CH4_INT | Level |
78 | AHB_DMA | AHB_DMA0_CH5_INT | Level |
79 | UART | UA2_INT | Level |
80 | UART | UA3_INT | Level |
81 | UART | UA7_INT | Level |
82 | AHB_DMA | AHB_DMA0_CH6_INT | Level |
83 | AHB_DMA | AHB_DMA0_CH7_INT | Level |
84 | UART | UA6_INT | Level |
85 | Key_Scan | SAR_INT | Level |
86 | Touch_Panel | RES_TOUCH_INT | Edge |
87 | I2C9 | I2C9_INT | Level |
88 | AHB_DMA | AHB_DMA1_CH0_INT | Level |
89 | USB30C0 | USB30C0_INT | Level |
90 | AHB_DMA | AHB_DMA1_CH1_INT | Level |
91 | USBC0 | USBC0_OTG_INT | Level |
92 | USBC0 | USBC0_DEVICE_INT | Level |
93 | USBC0 | USBC0_EHCI_INT | Level |
94 | USBC0 | USBC0_OHCI_INT | Level |
95 | STC_AV4 | STC_AV4_INTERRUPT_TIMERW | Level |
96 | STC_AV4 | STC_AV4_INTERRUPT_TIMER0 | Edge |
97 | STC_AV4 | STC_AV4_INTERRUPT_TIMER1 | Edge |
98 | STC_AV4 | STC_AV4_INTERRUPT_TIMER2B | Edge |
99 | STC_AV4 | STC_AV4_INTERRUPT_TIMER3B | Edge |
100 | U3PHY | U3PHY0_INT | Level |
101 | AHB_DMA | AHB_DMA1_CH2_INT | Level |
102 | AHB_DMA | AHB_DMA1_CH3_INT | Level |
103 | AHB_DMA | AHB_DMA1_CH4_INT | Level |
104 | AHB_DMA | AHB_DMA1_CH5_INT | Level |
105 | AHB_DMA | AHB_DMA1_CH6_INT | Level |
106 | AHB_DMA | AHB_DMA1_CH7_INT | Level |
107 | Reserved |
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