This experiment uses the FPGA daughter board and extended test daughter board supporting the Plus1 7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses the XILINX Vivado integrated development environment (version number 2018.3); in order to facilitate the user to verify the IP It is convenient to connect to the SOC system for verification. This experiment provides the corresponding basic files, as follows
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5.6.1 Vivado software installation
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There are two input clocks for the FPGA daughter board used in this experiment: All the way is the 25M clock GCLK that comes with the FPGA board. There are relevant constraints in the fpgasoc_top.xdc constraint file: create_clock -period 40.000 -name GCLK -waveform {0.000 20.000} [get_ports GCLK] After accessing FPGA, use its internal PLL IP to generate the FBIO Bus Bridge TX clock io_clk, reference clock ref_clk and system clock sysclk required by the project; the corresponding source file structure is as follows
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The other way is the FBIO RX 36M clock of the FBIO BUS Bus Bridge connected to the FPGA; there are related constraints in the fpgasoc_top.xdc constraint file:
create_clock -period 27.000 -name rclk -waveform {0.000 12.500} [get_ports {FPGA_PAD [35]}] The following introduces the use of its internal PLL IP after GCLK is connected to the FPGA to generate the clock required by the project. Refer to the figure below, double-click the red box to start the PLL setting operation
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The three clocks required for the PLL output project are described as follows: clk_out1 / clk_out2 is required for the FBIO Bus Bridge module. In this experiment, clk_out1 is 36M. The user can change the transmission speed of FBIO Bus Bridge TX / RX by modifying the settings; clk_out3 is the system clock 65M running on the FPGA daughter board;
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5.6.4 Reset settings of FPGA experiment project
Through FBIO BUSBus Bridge, connect the reset signal generated from SP7021 CPU to FPGA FPGA_PAD [18]; The aim_reset_sync.v module and performs synchronization processing to generate the reset signal sysrstn required by the FPGA system. The corresponding source file structure is as follows
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5.6.5 Constraint file setting for FPGA experiment project
In order to make the timing of the design meet the requirements, it is necessary to carry out timing-related constraints on the design. The corresponding source file structure is as follows
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Analysis of fpgasoc_top.xdc is as follows:
FPGA input clock input constraints
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_apb_bus_m32_bridge_0/FPGA_PAD_IOBUFIBUF[35]_inst/O]
FPGA system pin assignment
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set_property IOSTANDARD LVCMOS33 [get_ports FPGA_LED*]
FPGA 编程相关配置，用户不需要修改Note:FPGA programing related configure information，do not modify
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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