Disclaimer
...
CPU: Quad ARM Cortex-A55
1.8 GHz (2.1 GHz for specific components)
Cache
L1 Cache: 32kB I-cache / 32kB D-cache
L2 Cache: 128kB
L3 Cache: 1MB
Support NEON advance SIMD architecture & Floating-point
Support DVFS
0.5GHz ~1.5GHz @0.8V 85°C18GHz for SP7350
0.5GHz ~1.8GHz @TT 0.84V 85°C1.5GHz ~1.8GHz @SS 0.94V 85°C.5GHz for SP7350L
Support individual core power down
Support 2/4 core configurable by e-fuse (OTP)
Support maximum frequency limited by e-fuse (OTP)
Maximum limited to 1.5GHz, 1.8GHz, and 2.1 GHz
Support Coresight debug solution
JTAG interface
CTI and PMU
ETB: 1k to 4k bytes buffer size per core
NPU: AI and Parallel Processing Engine
Verisilicon VIP9000Nano-Di+, with 256kB SRAMUp to 4.1 TOPS (@900MHz) computing power
Support configurable operating frequency
Support individual controllable power domain.
Support OpenCL and OpenVX with Neural Network Extension
MCU: ARM Cortex-M4
Support FPU
Support 400MHz, 200MHz, 100MHz and 25MHz
Support JTAG and SWD interface
DDR SDRAM
LPDDR4-3200, DDR4-3200, LPDDR3/DDR3/DDR3L-1866
2 channels, 16 bits per channel
Up to 8GB memory capacity
Support IO retention
Internal SRAM
256kB at main power domain
384kB at CM4 (AO) power domain
For CM4 operation and DRAM IO retention data
AXI DMA
Support 16 channels
Support memory-to-memory copy
Support hardware handshake for 8-bit NAND controller
AHB DMA
Support 16 channels
Support memory-to-memory copy
Support hardware handshake for I2C and SPI controllers
Boot Devices
eMMC device
Support both 1.8V and 3.3V IOVDD
Support SDR up to 200 MHz (only for IOVDD = 1.8V)
Support DDR up to 160 MHz (only for IOVDD = 1.8V)
SD card
Support SD 3.0
Support SDR up to 200MHz
SPI-NAND flash
Support SLC NAND only
Support up to 150Mz (only for 1.8V)
Support 1 or 2 planes 2k page-size dice
Support 1 plane 4k page-size dice
8-bit NAND flash
Support 1.8V and 3.3V
Support 2k/4k/8 page-size dice
Support synchronous mode
SPI-NOR flash
Support 1/2/4-bit mode
Support 1.8V and 3.3V
Support up to 100Mz (only for 1.8V)
In-system Programming for Flash Devices
eMMC, SPI-NAND, 8-bit NAND, and SPI-NOR
In-system programming through USB flash drives or SD cards
Security
Support AES-128/192/256 encryption and decryption ECB, CBC, CTR mode
Support RSA
256/512/1024/2048 bits encryption
modular exponentiation
Support HASH
SHA-2 256/512
SHA-3 224/256/384/512
MD5
GHASH for AES GCM mode
Support POLY 1305
Support Pseudo RNG
Support ARM TZC-400
Support secure boot
SDIO
Support SD 3.0
Support transfer rate up to 104MB/s (UHS-1)
Video and image codec
H.264/MVC, VP8 and JPEG encoding
H.264/SVC and JPEG decoding
Individual controllable power domain.
USB3.1 (Gen. 1) Interface
Compliant to USB 3.1 Gen1 with DRD
Data rate up to 5Gbps
Integrated PHY
Support 4 sets of end-points (1 control and 3 data)
USB2.0 Interface
Compliant to USB 2.0
Support OTG 1.0
Support High, Full and Low speeds
4 in: 3 bulk/interrupt; 1 bulk/interrupt/isochronous
4 out: bulk/interrupt; 1 bulk/interrupt/isochronous
MIPI CSI RX
1 MIPI-CSI2 RX 4D1C (1.5 Gbps per lane), support 4 virtual channel
1 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel
2 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel
Shared pins with CPIO (when CPIO disable, MIPI CSI RX enable)
2 MIPI-CSI2 RX can be combined as 1 MIPI-CSI2 RX 4D1C, support 4 virtual channel
Max resolution: 2688x1944
MIPI CSI/DSI TX
One MIPI TX output for either CSI or DSI
4 lanes with 1.5Gbps per lane
DSI TX resolution up to 1920x1080
CSI TX resolution up to 3840x2880
Audio Interfaces
One bidirectional I2S
Two unidirectional I2S
One 16-channel TDM
Configurable serial clock frequency
Support 16 bit audio format
Support both master and slave mode
Compliant with the IIS/PCM standard
Ethernet Controller
Support 10/100/1000 Mbps data rate
Support RGMII and RMII interface (1.8V)
Support IEEE1588
ADC
12-bit SAR ADC with 4-channel
Sampling rate up to 1MHz
PWM
Support 12 bits resolution
Support pre-scaling factor from 1 to 512
Real-Time-Clock (RTC)
Independent Always-On power domain
64 bits free-run timer with 32.768 kHz clock input
SPI/I2C/UART
Up to seven UART interfaces
Up to six SPI interfaces (5 master, and 1 slave)
Up to ten I2C interfaces
GPIO
Support total 106 GPIOs
Support software programmable driving strength for all GPIOs
Support 60 GPIOs with 1.8V/3.3V capability
3 groups in AO-power domain
2 groups in main-power domain
Watchdog Timer
32-bit counter
Up to 223 second
Mailbox
For inter-processor communication between CA55 and CM4
RTC
32.768 kHz crystal
Semaphore
Support read lock and write unlock
Support 16 channels
Thermal Sensor
Placed at between CPU and NPU
Support two threshold temperatures (default disable)
Alarm threshold, interrupt to CPU
Shutdown threshold, for resetting all system
Multi-Function Interface (MFI) and CPIO
Selectable proprietary CPIO and MIPI CSI-RX interfaces
CPIO interface
Supports 4 data lanes for both TX and RX, provides 1.0 GiB/s bandwidth
Support hardware auto calibration
Support hardware auto and/or software programmable SWAP and CROSSOVER modes
Support data swap
Package: 15x15mm2 FCCSP
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One of the endpoints 1, 2, 3, and 4 can be configured for Isochronous mode, while the others can be configured as Bulk or Interrupt mode.
Similarly, one of the endpoints 5, 6, 7, and 8 can be configured for Isochronous mode, while the remaining endpoints can be configured for Bulk or Interrupt mode.
Here's the breakdown:
Endpoint # | Direction | Endpoint Type |
|---|---|---|
0 | In / Out | Control |
1 | In | INT or Bulk or ISO |
2 | In | INT or Bulk or ISO |
3 | In | INT or Bulk or ISO |
4 | In | INT or Bulk or ISO |
5 | Out | INT or Bulk or ISO |
6 | Out | INT or Bulk or ISO |
7 | Out | INT or Bulk or ISO |
8 | Out | INT or Bulk or ISO |
...
The following table illustrates the pin connections for both RGMII (GMAC_PHYSEL = 0) and RMII (GMAC_PHYSEL = 1) interfaces. It's important to note that SP7350 only supports 1.8V PHY, regardless of the selected interface type.
Ball Name | RGMII | RMII |
|---|---|---|
G_MX3 | PHY_RXC | |
G_MX4 | PHY_RXDV | PHY_CRS_DV |
G_MX5 | PHY_RXD0 | PHY_RXD0 |
G_MX6 | PHY_RXD1 | PHY_RXD1 |
G_MX7 | PHY_TXD0 | PHY_TXD0 |
G_MX8 | PHY_TXD1 | PHY_TXD1 |
G_MX9 | RGMII_MDC | RMII_MDC |
G_MX10 | PHY_TXC | PHY_REF_CLK |
G_MX11 | PHY_TXEN | PHY_TXEN |
G_MX12 | RGMII_MDIO | RMII_MDIO |
G_MX13 | PHY_RXD2 |
|
G_MX14 | PHY_RXD3 |
|
G_MX15 | PHY_TXD2 |
|
G_MX16 | PHY_TXD3 |
|
...
Channel | Data Lane # | Virtual Channel # | Remarks |
|---|---|---|---|
RX0 | 2 | 2 | Not available in this package |
RX1 | 2 | 2 | Not available in this package |
RX2 | 2 | 2 | |
RX3 | 2 | 2 | Not available for version A chips. |
RX4 | 2 | 2 | |
RX5 | 4 | 4 |
It's important to note that RX2 and RX3 share pins with the CPIO interface. Therefore, only one of RX2/RX3 or the CPIO interface can be active at any given time.
...
The GPIO pins of SP7350 are organized into 10 distinct groups, each with its dedicated power supply. Refer to the table below for a breakdown of the power domains, supplying voltages, hardware pin names, and the corresponding supplying power pins for all IO pins of SP7350:
GPIO # | Power Domain | Type | Pin Name | Power-supply Pin |
|---|---|---|---|---|
0 - 19 | Main | 1.8V GPIO | G_MX0 - G_MX19 | VDDPST18_GPIO |
20 | 1.8V/3.2V DVIO | G_MX20 | VDDPST3018_DVIO_2 | |
21 - 27 | G_MX21 - G_MX27 | VDDPST3018_DVIO_1 | ||
28 - 37 | G_MX28 - G_MX37 | VDDPST3018_DVIO_2 | ||
38 - 43 | SD Card | G_MX38 - G_MX43 | AVDDIO_3018_SD | |
44 - 49 | SDIO | G_MX44 - G_MX49 | AVDDIO_3018_SDIO | |
50 - 59 | CM4 (AO) | 1.8V/3.2V DVIO | AO_MX0 - AO_MX9 | VDDPST3018_DVIO_AO_1 |
60 - 69 | AO_MX10 - AO_MX19 | VDDPST3018_DVIO_AO_2 | ||
70 - 79 | AO_MX20 - AO_MX29 | VDDPST3018_DVIO_AO_3 | ||
80 - 98 | 1.8V GPIO | AO_MX30 - AO_MX48 | VDDPST18_GPIO_AO | |
99 - 105 | IV_MX0 - IV_MX6 |
...
14.2 Table of Default State of Power-on of GPIO
Ball Name | ST | DS[3:0] | SL | PE | PS | SPU | Remarks |
|---|---|---|---|---|---|---|---|
G_MX0 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX1 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
G_MX2 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
G_MX3 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
G_MX4 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-downup |
G_MX5 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX6 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX7 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX8 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX9 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
G_MX10 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
G_MX11 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX12 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX13 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX14 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX15 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX16 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX17 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX18 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
G_MX19 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX30 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX31 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX32 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX33 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX34 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX35 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX36 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX37 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
AO_MX38 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX39 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
AO_MX40 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX41 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
AO_MX42 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX43 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
AO_MX44 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
AO_MX45 | 1 | 1 | 1 | 1 | 0 | 0 | Pull-down |
AO_MX46 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX47 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
AO_MX48 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
IV_MX0 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
IV_MX1 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
IV_MX2 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
IV_MX3 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
IV_MX4 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
IV_MX5 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
IV_MX6 | 1 | 1 | 1 | 1 | 1 | 0 | Pull-up |
...
14.3 Table of Default State of Power-on of DVIO
Ball Name | ST | DS[3:0] | PU | PD | Remarks |
|---|---|---|---|---|---|
G_MX20 | 1 | 3 | 1 | 0 | Pull-up |
G_MX21 | 1 | 3 | 1 | 0 | Pull-up |
G_MX22 | 1 | 3 | 0 | 1 | Pull-down |
G_MX23 | 1 | 3 | 1 | 0 | Pull-up |
G_MX24 | 1 | 3 | 1 | 0 | Pull-up |
G_MX25 | 1 | 3 | 1 | 0 | Pull-up |
G_MX26 | 1 | 3 | 1 | 0 | Pull-up |
G_MX27 | 1 | 3 | 0 | 1 | Pull-down |
G_MX28 | 1 | 3 | 1 | 0 | Pull-up |
G_MX29 | 1 | 3 | 1 | 0 | Pull-up |
G_MX30 | 1 | 3 | 1 | 0 | Pull-up |
G_MX31 | 1 | 3 | 1 | 0 | Pull-up |
G_MX32 | 1 | 3 | 0 | 1 | Pull-down |
G_MX33 | 1 | 3 | 1 | 0 | Pull-up |
G_MX34 | 1 | 3 | 1 | 0 | Pull-up |
G_MX35 | 1 | 3 | 1 | 0 | Pull-up |
G_MX36 | 1 | 3 | 1 | 0 | Pull-up |
G_MX37 | 1 | 3 | 1 | 0 | Pull-up |
G_MX38 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX39 | 1 | 3 | 0 | 0 | Hi--Z |
G_MX40 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX41 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX42 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX43 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX44 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX45 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX46 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX47 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX48 | 1 | 3 | 0 | 0 | Hi-Z |
G_MX49 | 1 | 3 | 0 | 0 | Hi-Z |
AO_MX0 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX1 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX2 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX3 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX4 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX5 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX6 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX7 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX8 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX9 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX10 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX11 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX12 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX13 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX14 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX15 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX16 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX17 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX18 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX19 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX20 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX21 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX22 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX23 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX24 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX25 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX26 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX27 | 1 | 3 | 1 | 0 | Pull-up |
AO_MX28 | 1 | 3 | 0 | 1 | Pull-down |
AO_MX29 | 1 | 3 | 1 | 0 | Pull-up |
...
The SP7350 provides eight external interrupt inputs from configured GPIO pins. The table below lists the external interrupts 0 to 7 and the corresponding pins each interrupt can be configured with:
Ball Name | GPIO_INT0 | GPIO_INT1 | GPIO_INT2 | GPIO_INT3 | GPIO_INT4 | GPIO_INT5 | GPIO_INT6 | GPIO_INT7 |
|---|---|---|---|---|---|---|---|---|
G_MX1 | X1 | X1 | ||||||
G_MX2 | X2 | X2 | ||||||
G_MX3 | X3 | X3 | ||||||
G_MX4 | X4 | X4 | ||||||
G_MX5 | X5 | X5 | X1 | X1 | ||||
G_MX6 | X6 | X6 | X2 | X2 | ||||
G_MX7 | X3 | X3 | X1 | X1 | ||||
G_MX8 | X4 | X4 | X2 | X2 | ||||
G_MX9 | X5 | X5 | X3 | X3 | X1 | X1 | ||
G_MX10 | X6 | X6 | X4 | X4 | X2 | X2 | ||
G_MX11 | X7 | X7 | X5 | X5 | X3 | X3 | ||
G_MX12 | X6 | X6 | X4 | X4 | ||||
G_MX13 | X7 | X7 | X7 | X7 | X5 | X5 | ||
G_MX14 | X8 | X8 | X6 | X6 | ||||
G_MX15 | X9 | X9 | X7 | X7 | ||||
G_MX16 | X8 | X8 | X8 | X8 | ||||
G_MX17 | X9 | X9 | X9 | X9 | ||||
G_MX18 | X8 | X8 | X10 | X10 | ||||
G_MX19 | X9 | X9 | X11 | X11 |
...
Many GPIO (General Purpose Input/Output) pins offer alternative functions, providing versatility in their usage. These alternatives may consist of one, two, or more sets of output pins. For instance, I2C0 can be configured to output signals either at AO_MX4 (I2C0_CLK) and AO_MX5 (I2C0_DATA), or at AO_MX18 (I2C0_CLK) and AO_MX19 (I2C0_DATA). Below is a comprehensive table listing the alternatives for all GPIO pins:
Power Supply | Ball Name | GPIO | Function 1 | Function 2 | Function 3 | Function 4 |
|---|---|---|---|---|---|---|
VDDPST18_GPIO | G_MX0 | GPIO0 | GMAC_LPI_O | |||
G_MX1 | GPIO1 | CLKMCU (X1) | I2C6_CLK (X2) | |||
G_MX2 | GPIO2 | CLKWIFI (X1) | I2C6_DATA (X2) | |||
G_MX3 | GPIO3 | PHY_RXC | I2C7_CLK (X2) | |||
G_MX4 | GPIO4 | PHY_RXDV | I2C7_DATA (X2) | |||
G_MX5 | GPIO5 | PHY_RXD[0] | ||||
G_MX6 | GPIO6 | PHY_RXD[1] | ||||
G_MX7 | GPIO7 | PHY_TXD[0] | UA3_TXD (X2) | |||
G_MX8 | GPIO8 | PHY_TXD[1] | UA3_RXD (X2) |
| ||
G_MX9 | GPIO9 | RGMII_MDC | I2C8_CLK (X2) | SPI0_RXD (X2) | ||
G_MX10 | GPIO10 | PHY_TXC | I2C8_DATA (X2) | SPI0_SS (X2) | ||
G_MX11 | GPIO11 | PHY_TXEN | I2C9_CLK (X2) | SPI0_TXD (X2) | ||
G_MX12 | GPIO12 | RGMII_MDIO | I2C9_DATA (X2) | SPI0_CLK (X2) | ||
G_MX13 | GPIO13 | PHY_RXD[2] | CLKGENPHY (X1) | UADBG_TXD | CA55_TRSTN | |
G_MX14 | GPIO14 | PHY_RXD[3] | SPI1_RXD (X2) | UADBG_RXD | CA55_TMS | |
G_MX15 | GPIO15 | PHY_TXD[2] | SPI1_SS (X2) | CA55_TCK | ||
G_MX16 | GPIO16 | PHY_TXD[3] | SPI1_TXD (X2) | CA55_TDI | ||
G_MX17 | GPIO17 | SPI1_CLK (X2) | CA55_TDO | |||
G_MX18 | GPIO18 | UPHY0_DRV5V_ENB | ||||
G_MX19 | GPIO19 | UPHY0_ID | ||||
DVIO_2 | G_MX20 | GPIO20 | CARD0_SD_D[5] |
| PNAND_BUSY_B | |
DVIO_1 | G_MX21 | GPIO21 | SPI_NOR_D[2] | SPI_NAND_D[2] (X2) | PNAND_WP_B | |
G_MX22 | GPIO22 | SPI_NOR_CLK | SPI_NAND_CLK (X2) | PNAND_DQS_CLK | ||
G_MX23 | GPIO23 | SPI_NOR_D[1] | SPI_NAND_D[1] (X2) | PNAND_CE_B | ||
G_MX24 | GPIO24 | SPI_NOR_D[3] | SPI_NAND_D[3] (X2) | PNAND_RE_B | ||
G_MX25 | GPIO25 | SPI_NOR_CS_B | SPI_NAND_CS_B (X2) | PNAND_CLE | ||
G_MX26 | GPIO26 | SPI_NOR_D[0] | SPI_NAND_D[0] (X2) | PNAND_ALE | ||
G_MX27 | GPIO27 | CLKGNCMA (X1) | PNAND_WE_B | |||
DVIO_2 | G_MX28 | GPIO28 | CARD0_SD_D[3] | PNAND_DATA[0] | ||
G_MX29 | GPIO29 | CARD0_SD_D[4] | PNAND_DATA[1] | |||
G_MX30 | GPIO30 | CARD0_SD_D[0] | SPI_NAND_D[0] (X1) | PNAND_DATA[2] | ||
G_MX31 | GPIO31 | CARD0_SD_D[1] | SPI_NAND_D[2] (X1) | PNAND_DATA[3] | ||
G_MX32 | GPIO32 | CARD0_SD_CLK | SPI_NAND_CLK (X1) | PNAND_DQS | ||
G_MX33 | GPIO33 | CARD0_SD_D[2] | SPI_NAND_D[1] (X1) | PNAND_DATA[4] | ||
G_MX34 | GPIO34 | CARD0_SD_D[7] | SPI_NAND_D[3] (X1) | PNAND_DATA[5] | ||
G_MX35 | GPIO35 | CARD0_SD_D[6] | SPI_NAND_CS_B (X1) | PNAND_DATA[6] | ||
G_MX36 | GPIO36 | CARD0_SD_CMD | PNAND_DATA[7] | |||
G_MX37 | GPIO37 | CARD0_SD_DS | ||||
SD CARD | G_MX38 | GPIO38 | CARD1_SD_D[1] | |||
G_MX39 | GPIO39 | CARD1_SD_D[0] | ||||
G_MX40 | GPIO40 | CARD1_SD_CLK | ||||
G_MX41 | GPIO41 | CARD1_SD_CMD | ||||
G_MX42 | GPIO42 | CARD1_SD_D[3] | ||||
G_MX43 | GPIO43 | CARD1_SD_D[2] | ||||
SDIO | G_MX44 | GPIO44 | CARD2_SD_D[1] | SPI3_RXD (X1) | ||
G_MX45 | GPIO45 | CARD2_SD_D[0] | SPI3_SS (X1) | |||
G_MX46 | GPIO46 | CARD2_SD_CLK | SPI3_TXD (X1) | |||
G_MX47 | GPIO47 | CARD2_SD_CMD | SPI3_CLK (X1) | |||
G_MX48 | GPIO48 | CARD2_SD_D[3] | UA6_TXD (X2) | |||
G_MX49 | GPIO49 | CARD2_SD_D[2] | UA6_RXD (X2) | |||
DVIO_AO_1 | AO_MX0 | GPIO50 | UA0_TXD (X1) |
|
| |
AO_MX1 | GPIO51 | UA0_RXD (X1) |
|
|
| |
AO_MX2 | GPIO52 | UA1_TXD (X1) | CLKMCU (X2) | SPI3_RXD (X2) | ||
AO_MX3 | GPIO53 | UA1_RXD (X1) | CLKGNCMA (X2) | SPI3_SS (X2) | ||
AO_MX4 | GPIO54 | UA1_RTS_B (X1) | I2C0_CLK (X2) | SPI3_TXD (X2) | ||
AO_MX5 | GPIO55 | UA1_CTS_B (X1) | I2C0_DATA (X2) | SPI3_CLK (X2) | ||
AO_MX6 | GPIO56 | UA2_TXD (X1) | I2C2_CLK (X2) | AU1_BCK (X1) | ||
AO_MX7 | GPIO57 | UA2_RXD (X1) | I2C2_DATA (X2) | AU1_LRCK (X1) | ||
AO_MX8 | GPIO58 | UA2_RTS_B (X1) | PWM_CH0 (X2) | AU1_DATA0 (X1) | ADC1_DATA0 (X1) | |
AO_MX9 | GPIO59 | UA2_CTS_B (X1) | PWM_CH1 (X2) | |||
DVIO_AO_2 | AO_MX10 | GPIO60 | PWM_CH2 (X1) |
|
| |
AO_MX11 | GPIO61 | PWM_CH3 (X1) |
|
| ||
AO_MX12 | GPIO62 | UA3_TXD (X1) | CLKWIFI (X2) |
|
| |
AO_MX13 | GPIO63 | UA3_RXD (X1) | CLKRTC (X2) |
|
| |
AO_MX14 | GPIO64 | SPI0_RXD (X1) | UA1_TXD (X2) |
|
| |
AO_MX15 | GPIO65 | SPI0_SS (X1) | UA1_RXD (X2) |
|
| |
AO_MX16 | GPIO66 | SPI0_TXD (X1) | UA1_RTS_B (X2) |
|
| |
AO_MX17 | GPIO67 | SPI0_CLK (X1) | UA1_CTS_B (X2) |
|
| |
AO_MX18 | GPIO68 | I2C0_CLK (X1) | UA0_TXD (X2) |
|
| |
AO_MX19 | GPIO69 | I2C0_DATA (X1) | UA0_RXD (X2) |
|
| |
DVIO_AO_3 | AO_MX20 | GPIO70 | I2C1_CLK (X1) |
|
|
|
AO_MX21 | GPIO71 | I2C1_DATA (X1) |
| EXT_DAC_XCK1 | ||
AO_MX22 | GPIO72 | SPI4_RXD (X1) | SPI5_RXD (X2) | AU_BCK (X2) | ||
AO_MX23 | GPIO73 | SPI4_SS (X1) | SPI5_SS (X2) | AU_LRCK (X2) | ||
AO_MX24 | GPIO74 | SPI4_TXD (X1) | SPI5_TXD (X2) | ADC_DATA0 (X2) | ||
AO_MX25 | GPIO75 | SPI4_CLK (X1) | SPI5_CLK (X2) | AU_DATA0 (X2) | ||
AO_MX26 | GPIO76 | I2C2_CLK (X1) | UA2_TXD (X2) |
|
| |
AO_MX27 | GPIO77 | I2C2_DATA (X1) | UA2_RXD (X2) |
|
| |
AO_MX28 | GPIO78 | PWM_CH0 (X1) | UA2_RTS_B (X2) |
|
| |
AO_MX29 | GPIO79 | PWM_CH1 (X1) | UA2_CTS_B (X2) |
|
| |
GP1 | AO_MX30 | GPIO80 | UA6_TXD (X1) | SPI1_RXD (X1) | AU2_BCK (X1) | |
AO_MX31 | GPIO81 | UA6_RXD (X1) | SPI1_SS (X1) | AU2_LRCK (X1) | ||
AO_MX32 | GPIO82 | UA7_TXD (X1) | SPI1_TXD (X1) | AU2_DATA0 (X1) | ADC2_DATA0 (X1) | |
AO_MX33 | GPIO83 | UA7_RXD (X1) | SPI1_CLK (X1) | EXT_DAC_XCK_TM | CLKGENPHY (X2) | |
AO_MX34 | GPIO84 | I2C6_CLK (X1) | ||||
AO_MX35 | GPIO85 | I2C6_DATA (X1) | ||||
AO_MX36 | GPIO86 | I2C7_CLK (X1) | ||||
AO_MX37 | GPIO87 | I2C7_DATA (X1) | ||||
AO_MX38 | GPIO88 | I2C3_CLK (X1) | SPI2_RXD (X1) | CM4_TRSTN | ||
AO_MX39 | GPIO89 | I2C3_DATA (X1) | SPI2_SS (X1) | CM4_TMSSWD | ||
AO_MX40 | GPIO90 | I2C4_CLK (X1) | SPI2_TXD (X1) | CM4_SWCLKTCK | ||
AO_MX41 | GPIO91 | I2C4_DATA (X1) | SPI2_CLK (X1) | CM4_SWDO | ||
AO_MX42 | GPIO92 | I2C5_CLK (X1) | PWM_CH2 (X2) | CM4_TDI | ||
AO_MX43 | GPIO93 | I2C5_DATA (X1) | PWM_CH3 (X2) | CM4_TDO | TDMTX_XCK_TM | |
AO_MX44 | GPIO94 | I2C8_CLK (X1) | SPI5_RXD (X1) | AU_BCK (X1) | TDMTX_BCK | |
AO_MX45 | GPIO95 | I2C8_DATA (X1) | SPI5_SS (X1) | AU_LRCK (X1) | TDMTX_SYNC | |
AO_MX46 | GPIO96 |
| SPI5_TXD (X1) | ADC_DATA0 (X1_ | TDMTX_DATA16 | |
AO_MX47 | GPIO97 | I2C9_CLK (X1) | SPI5_CLK (X1) | AU_DATA0 (X1) | TDMTX_DATA16_O | |
AO_MX48 | GPIO98 | I2C9_DATA (X1) |
|
|
| |
GP2 | IV_MX0 | GPIO99 |
|
|
| |
IV_MX1 | GPIO100 |
|
| |||
IV_MX2 | GPIO101 |
|
| |||
IV_MX3 | GPIO102 |
|
| |||
IV_MX4 | GPIO103 |
|
| |||
IV_MX5 | GPIO104 |
|
| |||
IV_MX6 | GPIO105 |
|
|
...
15 Recommended Operating Conditions
15.1 Power Supply
Parameter Description | Power Name | Min. | Typ. | Max. | Unit | Comments |
|---|---|---|---|---|---|---|
Power for PLL | AVDD08_PLLC AVDD08_PLLD AVDD08_PLLS | 0.76 | 0.80 | 0.84 | V |
|
Power for SDIO | AVDD30_SD_SDIO | 3.04 | 3.20 | 3.36 | V |
|
Power for DDRPHY PLL | BP_VAA | 1.71 | 1.80 | 1.89 | V |
|
Power for DRAM controller | DRAM_VDD | 0.76 | 0.80 | 0.84 | V |
|
Power for DRAM IO pins | DRAM_VDDQ | 1.06 1.14 1.14 1.29 1.43 | 1.10 1.20 1.20 1.35 1.50 | 1.15 1.26 1.26 1.41 1.57 | V V V V V | LPDDR4 DDR4 LPDDR3 DDR3L DDR3 |
Power for CPIO | CPIOR_AVDD08 | 0.76 | 0.80 | 0.84 | V | |
Power for CPIO | CPIOR_AVDD10 | 1.71 | 1.80 | 1.89 | V | |
Power for MIPI RX | MIPI4_AVDD08 MIPI5_AVDD08 | 0.76 | 0.80 | 0.84 | V |
|
Power for MIPI RX | MIPI4_AVDD18 MIPI5_AVDD18 | 1.71 | 1.80 | 1.89 | V |
|
Power for MIPI TX | MIPITX_AVDD18 | 1.71 | 1.80 | 1.89 | V | |
Power for ADC | SAR12B_AVDD18 | 1.71 | 1.80 | 1.89 | V |
|
Power for thermal sensor | TML_AVDD18 | 1.17 | 1.80 | 1.89 | V |
|
Power for USB2 | USB20_AVDD18 | 1.71 | 1.80 | 1.89 | V |
|
Power for USB2 | USB20_AVDD33 | 3.14 | 3.30 | 3.46 | V |
|
Power for USB3 | USB3_AVDD08 | 0.76 | 0.80 | 0.84 | V |
|
Power for USB3 | USB3_DVDD08 | 0.76 | 0.80 | 0.84 | V |
|
Power for USB3 | USB3_VDD33 | 3.14 | 3.30 | 3.46 | V |
|
Power for digital core | VDD | 0.76 | 0.80 | 0.84 | V |
|
Power for Always-On digital core | VDD_AO | 0.76 | 0.80 | 0.84 | V |
|
Power for video codec | VDD_BLOCKA | 0.76 | 0.80 | 0.84 | V |
|
Power for CPU | VDD_CA55 | 0.80 | 0.84 | 0.88 |
|
|
Power for NPU | VDD_NPU | 0.80 | 0.84 | 0.88 | V |
|
Power for GPIO | VDDPST18_GPIO_0 VDDPST18_GPIO_1 VDDPST18_GPIO_AO VDDPST18_GPIO_RTC | 1.71 | 1.80 | 1.89 | V |
|
Power for Dual Voltage GPIO | VDDPST3018_DVIO_1 VDDPST3018_DVIO_2 VDDPST3018_DVIO_AO_1 VDDPST3018_DVIO_AO_2 VDDPST3018_DVIO_AO_3 | 32.0485 / 1.71 | 3.20 / 1.80 | 3.36 / 1.89 | V | Support two voltage levels |
Power for crystal | X32K_AVDD18 | 1.71 | 1.80 | 1.89 | V |
|
...
16.1 Absolute Maximum Ratings
Symbol | Parameter | Value | Unit |
|---|---|---|---|
VDD33 | Supply voltage 3.3V | 3.63 | V |
VDD_CA55 | Supply voltage 0.85V for CA55 | 1.05 | V |
VDD_NPU | Supply voltage 0.85V for NPU | 0.89 | V |
VDD08 | Supply voltage 0.8V for DRAM, video codec, chip top system, CM4 (AO) and RTC power domain, and other 0.8V for analog core power | 0.88 | V |
VDD18 | Supply voltage 1.8V | 1.98 | V |
VDD11 | Supply voltage 1.1V | 1.17 | V |
VDD30 | Supply voltage 3.0V | 3.46465 | V |
VO33 | Output voltage 3.3V | 3.63 | V |
VO18 | Output voltage 1.8V | 1.98 | V |
VI33 | 3.3V input voltage (3.3V tolerant inputs) | -0.3 ~ VDD33+0.3 | V |
VI18 | 1.8V input voltage | -0.3 ~ VDD18+0.3 | V |
TJ | Junction temperature | 120 | °C |
TSTG | Storage temperature | -40 ~ 150 | °C |
...
16.4.8 USB2.0 PHY Specification
16.4.8.1 Transmitter
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
VIH | High input level | Classic (FS) | 2.0 | V | ||
VIL | Low input level | Classic (FS) | 0.8 | V | ||
ROUT | Output resistance | Classic mode (Vout= 0 or 3.3V) | 40.5 | 45 | 49.5 | Ω |
HS mode (Vout = 0 to 800mV) | 40.5 | 45 | 49.5 | Ω | ||
COUT | Output capacitance | Seen from D+ or D- | 3.5 | 4.5 | pF | |
VM | Output common mode voltage | Classic (FS) mode | 1.485 | 1.65 | 1.8 | V |
HS mode | 0.18 | 0.2 | 0.22 | V | ||
VOH | Differential output signal high | Classic (FS); Io = 0mA | 2.97 | 3.3 | 3.63 | V |
Classic (FS); Io = 6mA | 2.71 | 3.05 | 3.38 | V | ||
HS mode; Io = 0mA | 360 | 400 | 440 | mV | ||
VOL | Differential output signal low | Classic (FS); Io = 0mA | 0 | - | 0.3 | V |
Classic (FS); Io = 6mA | -0.166 | -0.155 | -0.144 | V | ||
HS mode; Io = 0mA | -10 | 0 | 10 | mV |
...
16.4.9 USB3.1 PHY Specification
16.4.9.1 Transmitter
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
VTX-DIFF-PP | Differential TXP-P voltage swing |
| 0.8 | 1.0 | 1.2 | V |
VTX-DIFF-PP-LOW | Low-power differential |
| 0.4 | N/A | 1.2 | V |
VTX-DE-RATIO | TX de-emphasis |
| 0.4 | N/A | 1.2 | V |
RTX-DIFF-DC | DC differential impedance |
| 72 | N/A | 120 | Ω |
VTX-RCV-DETECT | The amount of voltage change allowed during receiver detection |
| N/A | N/A | 0.6 | V |
CAC-COUPLING | AC Coupling Capacitor |
| 75 | N/A | 265 | nF |
VTx-CM-IDLE-DELTA | Transmitter idle common-mode voltage change |
| 600 | N/A | -600 | mV |
TCDR_SLEW_MAX | Maximum slew-rate |
| N/A | N/A | 10 | mS/S |
16.4.9.2 Receiver
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
RRX-DC | Receiver DC common mode impedance |
| 18 | N/A | 30 | Ω |
RRX-DIFF-DC | DC differential impedance |
| 72 | N/A | 120 | Ω |
VRX-LFPS-DET-DIFFp-p | LFPS detect threshold |
| 100 | N/A | 300 | mV |
CRX-AC-COUPLING | AC coupling capacitor |
| 297 | N/A | 363 | nF |
VRX-DIFF-PP-POST-EQ | Differential RX peak-to-peak voltage |
| 30 | N/A | N/A | mV |
CRX-PARASITIC | RX input capacitance for return loss |
| N/A | N/A | 1.1 | pF |
VRX- CM-DC-ACTIVEIDLE- | RX AC common mode voltage during the U1 to U0 transition |
| N/A | N/A | 200 | mV peak |
16.4.10 MIPI CSI RX PHY Specification
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
VIH | High input level | Classic (FS) | 2.0 | V | ||
VIL | Low input level | Classic (FS) | 0.8 | V | ||
ROUT | Output resistance | Classic mode (Vout = 0 or 3.3V) | 40.5 | 45 | 49.5 | Ω |
HS mode (Vout = 0 to 800mV) | 40.5 | 45 | 49.5 | Ω | ||
COUT | Output capacitance | Seen from D+ or D- | 3.5 | 4.5 | pF | |
VM | Output common mode voltage | Classic (FS) mode | 1.45 | 1.65 | 1.85 | V |
HS mode | 0.175 | 0.2 | 0.225 | V | ||
VOH | Differential output signal high | Classic (FS); Io = 0mA | 2.97 | 3.3 | 3.63 | V |
Classic (FS); Io = 6mA | 2.91 | 3 | 3.08 | V | ||
HS mode; Io = 0mA | 360 | 400 | 440 | mV | ||
VOL | Differential output signal low | Classic (FS); Io = 0mA | -0.33 | 0 | 0.33 | V |
Classic (FS); Io = 6mA | -0.42 | -0.34 | -0.31 | V | ||
HS mode; Io = 0mA | -40 | 0 | 40 | mV |
...
16.4.11.1 MIPI CSI RX High-Speed Mode
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
VCMRX(DC) | Common-mode voltage HS receive mode |
| 70 |
| 3301,2 | mV |
VIDTH | Differential input high threshold |
|
|
| 703 | mV |
|
|
| 404 | mV | ||
VIDTL | Differential input low threshold |
| -703 |
|
| mV |
| -404 |
|
| mV | ||
VIHHS | Single-ended input high voltage |
|
|
| 4601 | mV |
VILHS | Single-ended input low voltage |
| -401 |
|
| mV |
FCLK | Operating frequency |
| 80 |
| 1250 | MHz |
VTERM-EN | Single-ended threshold for HS termination enable |
|
|
| 450 | mV |
ZID | Differential input impedance |
| 80 | 100 | 125 | Ω |
...
16.4.12 Driving-strength Table of GPIO
DS[3:0] | Source Current (mA) | Sink Current (mA) | ||||
|---|---|---|---|---|---|---|
Min. | Typ. | Max. | Min. | Typ. | Max. | |
0 | 0.8 | 1.1 | 1.5 | 0.7 | 1.1 | 1.6 |
1 | 1.1 | 1.6 | 2.2 | 1.1 | 1.7 | 2.3 |
2 | 2.3 | 3.3 | 4.3 | 2.1 | 3.3 | 4.7 |
3 | 3.4 | 4.9 | 6.5 | 3.2 | 5.0 | 7.0 |
4 | 4.5 | 6.6 | 8.6 | 4.2 | 6.6 | 9.3 |
5 | 5.7 | 8.2 | 10.8 | 5.3 | 8.3 | 11.7 |
6 | 6.8 | 9.9 | 13.0 | 6.3 | 9.9 | 13.9 |
7 | 7.9 | 11.5 | 15.1 | 7.4 | 11.6 | 16.2 |
8 | 9.0 | 13.1 | 17.2 | 8.4 | 13.2 | 18.5 |
9 | 10.2 | 14.8 | 19.4 | 9.4 | 14.8 | 20.8 |
10 | 11.3 | 16.4 | 21.6 | 10.5 | 16.5 | 23.1 |
11 | 12.4 | 18.1 | 23.7 | 11.5 | 18.1 | 25.4 |
12 | 13.5 | 19.6 | 25.8 | 12.6 | 19.7 | 27.6 |
13 | 14.7 | 21.3 | 28.0 | 13.6 | 21.4 | 29.9 |
14 | 15.8 | 22.9 | 30.1 | 14.6 | 23.0 | 32.1 |
15 | 16.9 | 24.6 | 32.3 | 15.7 | 24.6 | 34.4 |
16.4.13 Driving-strength Table of DVIO
DS[3:0] | Source Current (mA) | Sink Current (mA) | ||||
|---|---|---|---|---|---|---|
Min. | Typ. | Max. | Min. | Typ. | Max. | |
0 | 1.9 | 5.1 | 9.9 | 4.0 | 6.2 | 8.6 |
1 | 2.8 | 7.6 | 14.8 | 6.0 | 9.3 | 12.9 |
2 | 3.7 | 10.1 | 19.8 | 8.1 | 12.5 | 17.1 |
3 | 4.6 | 12.6 | 24.7 | 10.1 | 15.6 | 21.4 |
4 | 5.6 | 15.2 | 29.7 | 12.1 | 18.7 | 25.7 |
5 | 6.5 | 17.7 | 34.6 | 14.1 | 21.8 | 29.9 |
6 | 7.4 | 20.2 | 39.5 | 16.1 | 24.9 | 34.2 |
7 | 8.3 | 22.7 | 44.3 | 18.1 | 27.9 | 38.4 |
8 | 9.3 | 25.2 | 49.3 | 20.1 | 31.0 | 42.7 |
9 | 10.2 | 27.7 | 54.2 | 22.1 | 34.1 | 46.9 |
10 | 11.1 | 30.3 | 59.1 | 24.1 | 37.2 | 51.1 |
11 | 12.0 | 32.8 | 64.0 | 26.1 | 40.3 | 55.3 |
12 | 13.0 | 35.3 | 68.9 | 28.1 | 43.4 | 59.5 |
13 | 13.9 | 37.8 | 73.7 | 30.1 | 46.4 | 63.8 |
14 | 14.8 | 40.3 | 78.6 | 32.1 | 49.5 | 67.9 |
15 | 15.7 | 42.7 | 83.4 | 34.1 | 52.6 | 72.1 |
...
16.5.1.2 SPI-NAND Timing Parameters (3.3V)
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
tCK | Clock cycle for SPI flash |
| 9.76 | 9.76 |
| nS |
tCKH | Clock high-level width for SPI flash |
| 4.88 | 4.88 |
| nS |
tCKL | Clock low-level width for SPI flash |
| 4.88 | 4.88 |
| nS |
tSLCH | SPI_NAND_CEN active setup time relative to SPI_NAND_CLK |
| 19.5 |
| nS | |
tDDLY | Write data output delay from SPI_CLK falling edge |
| 0 | 0 |
| nS |
tRDVLD | Read data valid time |
| 8 | nS |
16.5.1.3 SPI-NAND Timing Parameters (1.8V)
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
tCK | Clock cycle for SPI flash |
| 6.5 | 7.5 |
| nS |
tCKH | Clock high-level width for SPI flash |
| 3.25 | 3.75 |
| nS |
tCKL | Clock low-level width for SPI flash |
| 3.25 | 3.75 |
| nS |
tSLCH | SPI_NAND_CEN active setup time relative to SPI_NAND_CLK |
| 13 |
| nS | |
tDDLY | Write data output delay from SPI_CLK Falling edge |
| 0 | 0 |
| nS |
tRDVLD | Read data valid time |
| 8 | nS |
...
16.5.2.2 I2S Master AC Timing Parameters
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
TLR = 1/FS | LRCK period (1/FS) | 5.208 | 31.25 | µs | ||
FS | LRCK frequency | 32 | 192 | kHz | ||
TBCK = 1/ FBCK | BCK period | 81.38 | 488.28 | nS | ||
FBCK | BCK frequency | 2.048 | 12.288 | MHz | ||
TBCKL | BCK pulse width low | 244 | nS | |||
TBCKH | BCK pulse width high | 244 | nS | |||
TLRB | LRCK edge to BCK rising edge | 10 | nS | |||
TDINS | I2S_DIN set-up time | 10 | nS | |||
TDINH | I2S_DIN hold time | 10 | nS | |||
TDOUTS | I2S_DOUT set-up time | 10 | nS | |||
TDOUTH | I2S_DOUT hold time | 10 | nS | |||
Tsmd | XCK to BCK active edge delay | 0 | 15 | nS | ||
Timd | XCK to LRCK delay | 0 | 15 | nS |
...
16.5.4.1 NOR NAND Timing Parameters (3.3/1.8V)
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
tCK | Clock cycle for SPI NOR Flash |
| 9.76 | 9.76 |
| nS |
tCKH | Clock high-level width for SPI NOR Flash |
| 4.88 | 4.88 |
| nS |
tCKL | Clock low-level width for SPI NOR Flash |
| 4.88 | 4.88 |
| nS |
tSLCH | SPI_NOR_CEN active setup time relative to SPI_NOR_CLK |
| 19.5 |
| nS | |
tDDLY | Write data output delay from SPI_NOR_CLK falling edge |
| 0 | 2.50 |
| nS |
tRDVLD | Read data valid time |
| 8 | nS |
...
16.5.5.2 SD/SDIO (High-Speed) Timing Parameters
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
Fck2 | Clock frequency data transfer mode | High Speed | 0 |
| 50 | MHz |
TWL2 | Clock low time | High Speed |
| 12.1 |
| nS |
TWH2 | Clock high time | High Speed |
| 9.0 |
| nS |
TTLH2 | Clock rise time | High Speed |
| 1.5 |
| nS |
TTHL2 | Clock fall time | High Speed |
| 1.6 |
| nS |
TSU2 | Input set-up time | High Speed |
| 14.7 |
| nS |
TIH2 | Input hold time | High Speed |
| 4.3 |
| nS |
TODLY | Output delay time during data transfer mode | High Speed |
| 9.3 |
| nS |
TOH | Output hold time | High Speed |
| 9.5 |
| nS |
...
16.5.5.3 SD/SDIO (SDR Mode) Timing Parameters
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
Fck2 | Clock frequency data transfer mode | SDR mode | 0 |
| 200 | MHz |
| Clock duty | SDR mode | 30 | 48 | 70 | nS |
TTLH2 | Clock rise time | SDR mode |
| 0.8 |
| nS |
TTHL2 | Clock fall time | SDR mode |
| 0.65 |
| nS |
TSU2 | Input set-up time | SDR mode |
| 0.78 |
| nS |
TIH2 | Input hold time | SDR mode |
| 4.05 |
| nS |
TODLY | Output delay time during data transfer mode | SDR mode |
| 3.18 |
| nS |
TOH | Output hold time | SDR mode |
| 3.775 |
| nS |
...
16.5.5.5 SD/SDIO (DDR mode) Timing Diagram
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| Clock duty cycle | High Speed (DDR) | 45 | 49.6 | 55 | % |
TTLH | Clock rise time | High Speed (DDR) |
| 0.84 | nS | |
TTHL | Clock fall time | High Speed (DDR) |
| 0.64 | nS | |
TISU | Input set-up time (CMD, SDR) | High Speed (DDR) | 14.76 |
| nS | |
TIH | Input hold time (CMD, SDR) | High Speed (DDR) | 4.52 | nS | ||
TODLY | Output delay time during data transfer (CMD, SDR) | High Speed (DDR) | 2.7 | nS | ||
ToH | Output hold time (CMD, SDR) | High Speed (DDR) | 2.2 | nS | ||
TISUddr | Input set-up time (DAT, DDR) | High Speed (DDR) | 4.8 | nS | ||
TIHddr | Input hold time (DAT, DDR) | High Speed (DDR) | 4.24 | nS | ||
TODLYddr | Output delay time during data transfer (DAT, DDR) | High Speed (DDR) | 7.6 | nS |
...
16.5.6.2 eMMC (SDR Mode) Timing Parameters
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
FCK2 | Clock frequency data transfer mode | SDR mode | 0 |
| 50 | MHz |
| Clock duty | SDR mode | 30 | 50.5 | 70 | nS |
TTLH2 | Clock rise time | SDR mode |
| 0.8 |
| nS |
TTHL2 | Clock fall time | SDR mode |
| 0.7 |
| nS |
TSU2 | Input set-up time | SDR mode |
| 13.4 |
| nS |
TIH2 | Input hold time | SDR mode |
| 5.5 |
| nS |
TODLY | Output delay time during data transfer mode | SDR mode |
| 9.6 |
| nS |
TOH | Output hold time | SDR mode |
| 8.6 |
| nS |
...
16.5.6.4 eMMC (DDR mode) Timing Parameters
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| Clock duty cycle | High Speed (DDR) | 45 | 50.7 | 55 | % |
TWL | Clock low time | High Speed (DDR) |
| 9.4 |
| nS |
TWH | Clock High time | High Speed (DDR) |
| 9.2 |
| nS |
TTLH | Clock rise time | High Speed (DDR) |
| 0.8 |
| nS |
TTHL | Clock fall time | High Speed (DDR) |
| 0.7 |
| nS |
TISU | Input set-up time (CMD, SDR) | High Speed (DDR) |
| 14.2 |
| nS |
TIH | Input hold time (CMD, SDR) | High Speed (DDR) |
| 4.2 |
| nS |
TODLY | Output delay time during data transfer (CMD, SDR) | High Speed (DDR) |
| 9.1 |
| nS |
ToH | Output hold time (CMD, SDR) | High Speed (DDR) |
| 8.3 |
| nS |
tRISE | Signal rise time (CMD, SDR) | High Speed (DDR) |
| 0.8 |
| nS |
Tfall | Signal fall time (CMD, SDR) | High Speed (DDR) |
| 0.8 |
| nS |
TISUddr | Input set-up time (DAT, DDR) | High Speed (DDR) |
| 4.5 |
| nS |
TIHddr | Input hold time (DAT, DDR) | High Speed (DDR) |
| 4.5 |
| nS |
TODLYddr | Output delay time during Data Transfer (DAT, DDR) | High Speed (DDR) | 4.5 |
| 5.8 | nS |
tRISE | Signal rise time (DAT 0-7) | High Speed (DDR) |
| 1.0 |
| nS |
tFALL | Signal fall time (DAT 0-7) | High Speed (DDR) |
| 0.9 |
| nS |
...
16.5.7.8 8-bit NAND (DDR Mode) Timing Parameters — 1
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
TCH | CE# hold | DDR mode | 3 | 5.30 |
| nS |
TCAD | Command, address data delay | DDR mode | 25 | 330 |
| nS |
TCALH | ALE, CLE, W/R# hold | DDR mode | 3 | 4.60 |
| nS |
TCALS | ALE, CLE, W/R# setup | DDR mode | 3 | 4.88 |
| nS |
TCAH | DQ hold – command, address | DDR mode | 3 | 4.87 |
| nS |
TCK | Average CLK cycle time | DDR mode | 15 |
|
| nS |
TCKL | CLK cycle high | DDR mode | 0.43 |
| 0.57 | TCK |
TCKH | CLK cycle low | DDR mode | 0.43 |
| 0.57 | TCK |
...
16.5.8.2 SPI MOSI Timing Parameters
Symbol | Parameters | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
TLS1 | Time from CSB (10%) to SCK (90%). |
|
| 60.21 |
| nS |
TLS2 | Time from SCK (10%) to CSB 90%). |
|
| 39.47 |
| nS |
TCL | SCK low time. |
| 20 | 19.90 | 81918 | nS |
TCH | SCK high time. |
| 20 | 20.11 | 81918 | nS |
TSET | Time from changing MOSI (10%, 90%) to SCK (90%). |
| 5 | 21.97 |
| nS |
THOL | Time from SCK (90%) to changing MOSI (10%, 90%). |
| 15 | 18.32 |
| nS |
TLH | Time between SPI cycles, CSB at high level (90%). |
| 158 |
|
| nS |
...
16.5.9.2 I2C Timing parameters for Fast and Standard Mode
Symbol | Parameters | Standard Mode | Fast Mode | Unit |
|---|---|---|---|---|
|
| VDD = 1.8V |
| |
|
| MS = 1 |
| |
|
| 100kHz | 400kHz |
|
FSCL | SCL clock frequency | 99.41 | 396.8 | kHz |
TLOW | Low period of the SCL clock | 5.318 | 1.548 | µS |
THIGH | High period of the SCL clock | 4.680 | 0.9117 | µS |
THD;STA | Hold time (repeated) START condition | 4.718 | 0.9482 | µS |
TSU;STA | Set-up time for a repeated START condition | 5.390 | 1.020 | µS |
THD;DAT | Data hold time | 2.016 | 0.00681 | µS |
TSU;DAT | Data set-up time | 3246.0 | 1454.0 | nS |
Tr | Rise time of both SDA and SCL signals | CLK = 54.50 DATA = 54.67 | CLK = 56.00 DATA = 52.20 | nS |
Tf | Fall time of both SDA and SCL signals | CLK = 2.182 DATA = 2.628 | CLK = 2.267 DATA = 2.328 | nS |
TSU;STO | Set-up time for STOP condition | 4.808 | 1.040 | µS |
TVD;DAT | Data valid time | 2.072 | 0.0092 | µS |
TVD;ACK | Data valid acknowledge time | 0.177 | 0.177 | µS |
TBUF | Bus free time between a STOP and START condition | 29.30 | 29.07 | µS |
TSP | Pulse width of spikes that must be suppressed by the input filter |
|
| nS |
...
16.5.9.4 I2C Timing Parameters for High-speed Mode
Symbol | Parameters | High Speed Mode | Unit | |
|---|---|---|---|---|
|
| VDD = 1.8V | VDD = 3V |
|
|
| MS = 1 | MS = 0 |
|
|
| 1.7MHz | 1.7MHz |
|
FSCLH | SCLH clock frequency | 1.251 | 1.266 | MHz |
TLOW | Low period of the SCL clock | 437.6 | 432.7 | nS |
THIGH | High period of the SCL clock | 299.3 | 293.3 | nS |
THD;STA | Hold time (repeated) START condition | 427.6 | 425.4 | nS |
TSU;STA | Set-up time for a repeated START condition | 511.7 | 504.2 | nS |
THD;DAT | Data hold time | 28.03 | 24.37 | nS |
TSU;DAT | Data set-up time | 354.7 | 352.6 | nS |
TrCL | Rise time of SCLH signal | 55.33 | 53.33 | nS |
TrCL1 | Rise time of SCLH signal after a repeated START condition and after an acknowledge bit | 55.83 | 54.92 | nS |
TfCL | Fall time of SCLH signal | 2.491 | 4.807 | nS |
TrDA | Rise time of SDAH signal | 53.00 | 52.00 | nS |
TfDA | Fall time of SDAH signal | 2.663 | 4.833 | nS |
TSU;STO | Set-up time for STOP condition | 493.3 | 479.4 | nS |
...
Symbol | Parameters | Min. | Typ. | Max. | Unit |
t1 | RMII clock period |
| 20 |
| nS |
| RMII clock duty cycle | 35 |
| 65 | % |
t2 | TX_Data, TX_EN setup to RMII clock rising | 4 |
|
| nS |
t3 | TX_Data, TX_EN hold from RMII clock rising | 2 |
|
| nS |
t4 | RXD, CRSDV setup time | 2 |
|
| nS |
t5 | RXD, CRSDV hold time | 2 |
|
| nS |
16.6 Power Consumption
...
Symbol
...
Parameters
...
Conditions
...
Min.
...
Typ.
...
Max.
...
Unit
...
I08
I1.1
I1.8
I3.0
I3.3
...
0.8V supply current
1.1V supply current
1.8V supply current
3.0V supply current
3.3V supply current
Chip leakage is 182 mA @0.8V
including:
CA55 @1.8GHz,
NPU @900MHz with 0.85V
...
2675
280
42.5
65.5
199.5
...
4243
285
44.7
67
213.5
...
mA
mA
mA
mA
mA
...
Power Dissipation
...
3.38
...
4.69
...
W
Note: The power consumption is based on a chip with leakage current equals to 182 mA.
Note: The NPU and CA55 power is based on 0.85V.
Note: The test condition is defined by Vendor.
...
Powers | Nominal Voltage (V) | FF corner (average) | Sim (peak) | Unit | |
|---|---|---|---|---|---|
37°C | 120°C | 85°C | |||
DPHY_0V8 | 0.8 | 320 | 430 | 420 | mA |
MIPI_0V8 | 0.8 | 34 | 36 | 90 | mA |
SYS_0V8 | 0.8 | 363 | 550 | 2140 | mA |
VDD_CA55 | 0.85 | 895 | 1889 | 940 | mA |
VDD_NPU | 0.85 | 930 | 1078 | 5390 | mA |
VDD_VV | 0.8 | 262 | 397 | 1670 | mA |
VDDQ | 1.1 | 337 | 344 | mA | |
MIPI_1V8 | 1.8 | 10 | 12 | 19 | mA |
SYS_1V8 | 1.8 | 20 | 21 | mA | |
SYS_3V | 3.0 | 75 | 76 | mA | |
SYS_3V3 | 3.3 | 210 | 237 | mA | |
AO_0V8 | 0.8 | 45 | 80 | mA | |
AO_1.8V | 1.8 | 19 | 20 | mA | |
AO_3.0V | 3.0 | 10 | 10 | mA | |
Test conditions (worst case):
A chip with a CA55 (+L3) leakage current of 182 mA at 25°C.
CA55 runs at 1.8GHz, 0.85V, 70% duty
NPU runs at 900MHz, 0.85V, 50% duty
17. Ball Map
...
18. Ball Definition
...
AO: Always-On power domain
UA: UART
18.2 Ball Assignment
Ball No. | Ball Name | Function Type |
|---|---|---|
A2 | BP_A[30] | DRAM address and command |
A4 | BP_A[27] | DRAM address and command |
A6 | BP_A[25] | DRAM address and command |
A8 | BP_A[21] | DRAM address and command |
A10 | BP_A[17] | DRAM address and command |
A12 | BP_A[4] | DRAM address and command |
A14 | BP_A[15] | DRAM address and command |
A16 | BP_A[12] | DRAM address and command |
A18 | BP_A[9] | DRAM address and command |
A20 | BP_A[6] | DRAM address and command |
A22 | BP_D[14] | DRAM data and strobe |
A23 | BP_D[13] | DRAM data and strobe |
A25 | BP_D[22] | DRAM data and strobe |
A27 | BP_D[20] | DRAM data and strobe |
A29 | BP_D[17] | DRAM data and strobe |
A31 | AO_MX28 | GPIO, PWM0, UA2 in AO domain |
A33 | AO_MX25 | GPIO, SPI4, SPI5 in AO domain |
A35 | AO_MX23 | GPIO, SPI4, SPI5 in AO domain |
B1 | BP_A[33] | DRAM address and command |
B2 | BP_A[31] | DRAM address and command |
B3 | BP_A[29] | DRAM address and command |
B4 | BP_A[28] | DRAM address and command |
B5 | BP_A[26] | DRAM address and command |
B6 | GND | GND |
B7 | BP_A[24] | DRAM address and command |
B8 | GND | GND |
B9 | BP_A[20] | DRAM address and command |
B10 | GND | GND |
B11 | BP_A[16] | DRAM address and command |
B12 | GND | GND |
B13 | BP_A[5] | DRAM address and command |
B14 | GND | GND |
B15 | BP_A[14] | DRAM address and command |
B16 | BP_A[13] | DRAM address and command |
B17 | BP_A[11] | DRAM address and command |
B18 | BP_A[10] | DRAM address and command |
B19 | BP_A[8] | DRAM address and command |
B20 | BP_A[7] | DRAM address and command |
B21 | GND | GND |
B22 | BP_D[15] | DRAM data and strobe |
B23 | BP_D[12] | DRAM data and strobe |
B24 | GND | GND |
B25 | BP_D[21] | DRAM data and strobe |
B26 | GND | GND |
B27 | BP_D[19] | DRAM data and strobe |
B28 | BP_D[18] | DRAM data and strobe |
B29 | BP_D[16] | DRAM data and strobe |
B30 | GND | GND |
B31 | AO_MX29 | GPIO, PWM1 or UA2 in AO domain |
B32 | AO_MX26 | GPIO, I2C2 or UA2 in AO domain |
B33 | AO_MX27 | GPIO, I2C2 or UA2 in AO domain |
B34 | AO_MX24 | GPIO, SPI4 or SPI5 in AO domain |
B35 | AO_MX22 | GPIO, SPI4 or SPI5 in AO domain |
B36 | AO_MX20 | GPIO or I2C1 in AO domain |
B37 | AO_MX21 | GPIO or I2C1 in AO domain |
C2 | BP_A[32] | DRAM address and command |
C36 | AO_MX18 | GPIO, I2C0 or UA0 in AO domain |
D1 | BP_A[35] | DRAM address and command |
D2 | BP_A[34] | DRAM address and command |
D36 | AO_MX17 | GPIO, SPI0 or UA1 in AO domain |
D37 | AO_MX16 | GPIO, SPI0 or UA1 in AO domain |
E2 | GND | GND |
E36 | AO_MX15 | GPIO, SPI0 or UA1 in AO domain |
F1 | BP_D[38] | DRAM data and strobe |
F2 | BP_D[39] | DRAM data and strobe |
F36 | AO_MX13 | GPIO or UA3 in AO domain |
F37 | AO_MX12 | GPIO or UA3 in AO domain |
G2 | BP_D[37] | DRAM data and strobe |
G36 | AO_MX11 | GPIO or PWM3 in AO domain |
H1 | BP_D[44] | DRAM data and strobe |
H2 | BP_D[36] | DRAM data and strobe |
H36 | AO_MX10 | GPIO or PWM2 in AO domain |
H37 | AO_MX9 | GPIO, UA2 or PWM1 in AO domain |
J2 | GND | GND |
J36 | AO_MX8 | GPIO, UA2 or PWM0 in AO domain |
K1 | BP_D[46] | DRAM data and strobe |
K2 | BP_D[45] | DRAM data and strobe |
K36 | AO_MX7 | GPIO, UA2 or I2C2 in AO domain |
K37 | AO_MX30 | GPIO, UA6 or SPI1 in AO domain |
L2 | GND | GND |
L36 | AO_MX33 | GPIO, UA7 or SPI1 in AO domain |
M1 | BP_D[42] | DRAM data and strobe |
M2 | BP_D[43] | DRAM data and strobe |
M36 | AO_MX31 | GPIO, or UA6 or SPI1 in AO domain |
M37 | AO_MX35 | GPIO or I2C6 in AO domain |
N1 | BP_D[41] | DRAM data and strobe |
N2 | BP_D[40] | DRAM data and strobe |
N36 | AO_MX34 | GPIO or I2C6 in AO domain |
P2 | GND | GND |
P36 | AO_MX44 | GPIO or SPI5 in AO domain |
P37 | AO_MX46 | GPIO, I2C8 or SPI5 in AO domain |
R1 | MIPITX_OUTN0 | MIPI TX |
R2 | MIPITX_OUTP0 | MIPI TX |
R36 | AO_MX45 | GPIO, I2C8 or SPI5 in AO domain |
T2 | MIPITX_AVSS | Analog GND to MIPI TX |
T36 | AO_MX39 | GPIO, I2C3 or SPI2 in AO domain |
T37 | AO_MX40 | GPIO, I2C4 or SPI2 in AO domain |
U1 | MIPITX_OUTP1 | MIPI TX |
U2 | MIPITX_OUTN1 | MIPI TX |
U36 | AO_MX37 | GPIO or I2C7 in AO domain |
V1 | MIPITX_CLKN | MIPI TX |
V2 | MIPITX_CLKP | MIPI TX |
V36 | AO_MX36 | GPIO or I2C7 in AO domain |
V37 | AO_MX38 | GPIO, I2C3 or SPI2 in AO domain |
W2 | MIPITX_AVSS | Analog GND to MIPI TX |
W36 | X32K_AVSS | Analog GND to 32K crystal |
Y1 | MIPITX_OUTN2 | MIPI TX |
Y2 | MIPITX_OUTP2 | MIPI TX |
Y36 | X32KI | 32.768kHz crystal in |
Y37 | X32KO | 32.768kHz crystal out |
AA2 | MIPITX_AVSS | Analog GND to MIPI TX |
AA36 | X32K_AVSS | Analog GND to 32K crystal |
AB1 | MIPITX_OUTP3 | MIPI TX |
AB2 | MIPITX_OUTN3 | MIPI TX |
AB36 | SAR12B_AVSS | Analog GND to SAR ADC |
AC2 | MIPI4_AVSS | Analog GND to MIPI #4 |
AC36 | SAR12B_ADI0 | ADC input #0 |
AC37 | SAR12B_ADI1 | ADC input #1 |
AD1 | MIPI4_DP[1] | MIPI RX #4 |
AD2 | MIPI4_DN[1] | MIPI RX #4 |
AD36 | SAR12B_ADI3 | ADC input #3 |
AD37 | SAR12B_ADI2 | ADC input #2 |
AE1 | MIPI4_SN | MIPI RX #4 |
AE2 | MIPI4_SP | MIPI RX #4 |
AE36 | SAR12B_AVSS | Analog GND to SAR ADC |
AF2 | MIPI4_AVSS | Analog GND to MIPI #4 |
AF36 | XTAL_AVSS | Analog GND 25M crystal |
AG1 | MIPI4_DP[0] | MIPI RX #4 |
AG2 | MIPI4_DN[0] | MIPI RX #4 |
AG36 | XIN | 25MHz Crystal in |
AG37 | XOUT | 25MHz Crystal out |
AH2 | MIPI4_AVSS | Analog GND to MIPI #4 |
AH36 | XTAL_AVSS | Analog GND to 25M crystal |
AJ1 | USB3_DM | USB3 |
AJ2 | USB3_DP | USB3 |
AJ36 | CPIOR_AVSS | Analog GND to CPIO |
AK2 | GND | GND |
AK36 | CPIOR-eRXD3P/MIPIRX2_DN3 | CPIO or MIPI RX #2 |
AK37 | CPIOR-eRXD3N/MIPIRX2_DP3 | CPIO or MIPI RX #2 |
AL1 | USB3_REFCLK_M | USB3 reference clock input, connect to GND |
AL2 | USB3_REFCLK_P | USB3 reference clock input, connect to GND |
AL36 | CPIOR-eTXD3P/MIPIRX2_DP1 | CPIO or MIPI RX #2 |
AL37 | CPIOR-eTXD3N/MIPIRX2_DN1 | CPIO or MIPI RX #2 |
AM2 | GND | GND |
AM36 | CPIOR_AVSS | Analog GND to CPIO |
AN1 | USB3_RX0P | USB3 |
AN2 | USB3_RX0M | USB3 |
AN36 | CPIOR-eTXD2N/MIPIRX2_CP | CPIO or MIPI RX #2 |
AN37 | CPIOR-eTXD2P/MIPIRX2_CN | CPIO or MIPI RX #2 |
AP2 | GND | GND |
AP36 | CPIOR-eRXD2N/MIPIRX2_DN0 | CPIO or MIPI RX #2 |
AP37 | CPIOR-eRXD2P/MIPIRX2_DP0 | CPIO or MIPI RX #2 |
AR1 | USB3_TX0P | USB3 |
AR2 | USB3_TX0M | USB3 |
AR36 | CPIOR_AVSS | Analog GND to CPIO |
AT2 | GND | GND |
AT3 | USB3_RX1M | USB3 |
AT4 | GND | GND |
AT5 | USB3_TX1M | USB3 |
AT6 | GND | GND |
AT7 | G_MX16 | GPIO, Ethernet MAC or SPI1 |
AT8 | G_MX15 | GPIO, Ethernet MAC or SPI1 |
AT9 | G_MX13 | GPIO, Ethernet MAC or UADBG |
AT10 | G_MX10 | GPIO, Ethernet MAC, SPI0 or I2C8 |
AT11 | G_MX8 | GPIO, Ethernet MAC or UA3 |
AT12 | G_MX3 | GPIO, Ethernet MAC or I2C7 |
AT13 | G_MX42 | GPIO or SD card |
AT14 | G_MX38 | GPIO or SD card |
AT15 | G_MX39 | GPIO or SD card |
AT16 | G_MX41 | GPIO or SD card |
AT17 | G_MX45 | GPIO, SDIO or SPI3 |
AT18 | G_MX46 | GPIO, SDIO or SPI3 |
AT19 | G_MX48 | GPIO, SDIO or UA6 |
AT20 | G_MX49 | GPIO, SDIO or UA6 |
AT21 | G_MX28 | GPIO, eMMC or 8-bit NAND |
AT22 | G_MX30 | GPIO, eMMC, SPI-NAND or 8-bit NAND |
AT23 | G_MX37 | GPIO or eMMC |
AT24 | G_MX36 | GPIO, eMMC or 8-bit NAND |
AT25 | G_MX31 | GPIO, eMMC, SPI-NAND or 8-bit NAND |
AT26 | G_MX32 | GPIO, eMMC, SPI-NAND or 8-bit NAND |
AT27 | G_MX33 | GPIO, eMMC, SPI-NAND or 8-bit NAND |
AT28 | CPIOR_AVSS | Analog GND to CPIO |
AT29 | CPIOR-eTXD0P | CPIO |
AT30 | CPIOR-eRXD0P/MIPIRX3_DN0 | CPIO or MIPI RX #3 |
AT31 | CPIOR_AVSS | Analog GND to CPIO |
AT32 | CPIOR-eRXD1N/MIPIRX3_CN | CPIO or MIPI RX #3 |
AT33 | CPIOR-eTXD1N/MIPIRX3_DP1 | CPIO or MIPI RX #3 |
AT34 | CPIOR_AVSS | Analog GND to CPIO |
AT35 | CPIOR-eTXCP | CPIO |
AT36 | CPIOR-eRXCP/MIPIRX2_DN2 | CPIO or MIPI RX #2 |
AT37 | CPIOR_AVSS | Analog GND to CPIO |
AU3 | USB3_RX1P | USB3 |
AU5 | USB3_TX1P | USB3 |
AU7 | G_MX17 | GPIO or SPI1 |
AU9 | G_MX14 | GPIO, Ethernet MAC, UADBG or SPI1 |
AU11 | G_MX7 | GPIO, Ethernet MAC or UA3 |
AU13 | G_MX43 | GPIO or SD card |
AU15 | G_MX40 | GPIO or SD card |
AU17 | G_MX44 | GPIO, SDIO or SPI3 |
AU19 | G_MX47 | GPIO, SDIO or SPI3 |
AU21 | G_MX29 | GPIO, eMMC or 8-bit NAND |
AU23 | G_MX20 | GPIO, eMMC or 8-bit NAND |
AU25 | G_MX35 | GPIO, eMMC, SPI-NAND or 8-bit NAND |
AU27 | G_MX34 | GPIO, eMMC, SPI-NAND or 8-bit NAND |
AU29 | CPIOR-eTXD0N | CPIO |
AU30 | CPIOR-eRXD0N/MIPIRX3_DP0 | CPIO or MIPI RX #3 |
AU32 | CPIOR-eRXD1P/MIPIRX3_CP | CPIO or MIPI RX #3 |
AU33 | CPIOR-eTXD1P/MIPIRX3_DN1 | CPIO or MIPI RX #3 |
AU35 | CPIOR-eTXCN | CPIO |
AU36 | CPIOR-eRXCN/MIPIRX2_DP2 | CPIO or MIPI RX #2 |
AV1 | BP_D[30] | DRAM data and strobe |
AV2 | BP_D[29] | DRAM data and strobe |
AV3 | GND | GND |
AV4 | BP_A[37] | DRAM address and command |
AV6 | BP_A[36] | DRAM address and command |
AV7 | BP_MEMRESET_L | DRAM Reset |
AV9 | BP_A[3] | DRAM address and command |
AV10 | BP_A[1] | DRAM address and command |
AV12 | GND | GND |
AV13 | BP_D[8] | DRAM data and strobe |
AV15 | GND | GND |
AV16 | BP_D[0] | DRAM data and strobe |
AV17 | BP_D[2] | DRAM data and strobe |
AV18 | GND | GND |
AV19 | VDDPST3018_DVIO_AO_3 | 3.2V or 1.8V supply for DVIO_AO_3 Group in AO domain |
AV20 | AO_MX19 | GPIO, I2C0 or UA0 in AO domain |
AW1 | BP_D[31] | DRAM data and strobe |
AW2 | GND | GND |
AW3 | BP_D[28] | DRAM data and strobe |
AW4 | BP_A[38] | DRAM address and command |
AW6 | BP_A[22] | DRAM address and command |
AW7 | BP_ZN | DRAM reference resistor |
AW9 | BP_A[18] | DRAM address and command |
AW10 | BP_A[2] | DRAM address and command |
AW12 | BP_D[4] | DRAM data and strobe |
AW13 | BP_D[7] | DRAM data and strobe |
AW15 | BP_D[9] | DRAM data and strobe |
AW16 | BP_D[1] | DRAM data and strobe |
AW17 | BP_D[3] | DRAM data and strobe |
AW18 | GND | GND |
AW19 | VDDPST18_DVIO_AO_3 | Connect to bypass capacitors |
AW20 | AO_MX14 | GPIO, SPI0 or UA1 in AO domain |
AY1 | BP_D[33] | DRAM data and strobe |
AY2 | BP_D[34] | DRAM data and strobe |
AY3 | GND | GND |
AY4 | BP_A[23] | DRAM address and command |
AY6 | BP_VAA | 1.8V analog supply to DDRPHY PLL |
AY7 | BP_ALERT_N | DRAM alert output |
AY9 | BP_VREF | DRAM VREF output |
AY10 | BP_A[0] | DRAM address and command |
AY12 | BP_D[5] | DRAM data and strobe |
AY13 | BP_D[6] | DRAM data and strobe |
AY15 | BP_D[10] | DRAM data and strobe |
AY16 | GND | GND |
AY17 | VDDPST18_DVIO_AO_2 | Connect to bypass capacitors |
AY18 | VDDPST3018_DVIO_AO_2 | 3.2V or 1.8V supply for DVIO_AO_2 Group in AO domain |
AY19 | AO_MX1 | GPIO or UA0 in AO domain |
AY20 | AO_MX5 | GPIO, UA1, I2C0 or SPI3 in AO domain |
BA1 | GND | GND |
BA2 | BP_D[32] | DRAM data and strobe |
BA3 | GND | GND |
BA4 | GND | GND |
BA5 | GND | GND |
BA6 | GND | GND |
BA7 | GND | GND |
BA8 | GND | GND |
BA9 | GND | GND |
BA10 | GND | GND |
BA11 | GND | GND |
BA12 | GND | GND |
BA13 | GND | GND |
BA14 | GND | GND |
BA15 | GND | GND |
BA16 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BA17 | VDDPST18_DVIO_AO_1 | Connect to bypass capacitors |
BA18 | VDDPST3018_DVIO_AO_1 | 3.2V or 1.8V supply for DVIO_AO_1 Group in AO domain |
BA19 | AO_MX4 | GPIO, UA1, I2C0 or SPI3 in AO domain |
BA20 | AO_MX6 | GPIO, UA2 or I2C2 in AO domain |
BB1 | BP_D[25] | DRAM data and strobe |
BB2 | BP_D[24] | DRAM data and strobe |
BB3 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB4 | GND | GND |
BB5 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB6 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB7 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB8 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB9 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB10 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB11 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB12 | GND | GND |
BB13 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB14 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB15 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BB16 | OTP_1V8 | 1.8V supply to write OTP |
BB17 | AO_MX0 | GPIO or UA0 in AO domain |
BB18 | AO_MX3 | GPIO, UA1 or SPI3 in AO domain |
BB19 | GND | GND |
BB20 | AO_MX2 | GPIO, UA1 or SPI3 in AO domain |
BC4 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BC5 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BC6 | GND | GND |
BC7 | GND | GND |
BC8 | GND | GND |
BC9 | DRAM_VDDQ | Supply to DRAM data and strobe pin |
BC10 | GND | GND |
BC11 | DRAM_VDD | 0.8V supply to DRAM digital core |
BC12 | DRAM_VDD | 0.8V supply to DRAM digital core |
BC13 | DRAM_VDD | 0.8V supply to DRAM digital core |
BC14 | GND | GND |
BC15 | GND | GND |
BD1 | GND | GND |
BD2 | BP_D[26] | DRAM data and strobe |
BD3 | BP_D[27] | DRAM data and strobe |
BD4 | GND | GND |
BD5 | DRAM_VDD | 0.8V supply to DRAM digital core |
BD6 | DRAM_VDD | 0.8V supply to DRAM digital core |
BD7 | DRAM_VDD | 0.8V supply to DRAM digital core |
BD8 | GND | GND |
BD9 | DRAM_VDD | 0.8V supply to DRAM digital core |
BD10 | DRAM_VDD | 0.8V supply to DRAM digital core |
BD11 | GND | GND |
BD12 | GND | GND |
BD13 | GND | GND |
BD14 | GND | GND |
BD15 | VDDPST18_GPIO_AO | 1.8V supply for GP1 and GP2 groups in AO domain |
BD16 | VDDPST18_GPIO_AO | 1.8V supply for GP1 and GP2 groups in AO domain |
BD17 | AO_MX47 | GPIO, I2C9 or SPI5 in AO domain |
BD18 | AO_MX48 | GPIO or I2C9 AO domain |
BD19 | GND | GND |
BD20 | AO_MX32 | GPIO, UA7 or SPI1 in AO domain |
BE1 | MIPITX_AVDD18 | 1.8V analog supply to MIPI TX |
BE2 | MIPITX_AVSS | Analog GND to MIPI TX |
BE5 | GND | GND |
BE6 | GND | GND |
BE7 | GND | GND |
BE8 | GND | GND |
BE9 | GND | GND |
BE10 | GND | GND |
BE11 | GND | GND |
BE12 | VDD_BLOCKA | 0.8V supply to video codec |
BE13 | VDD_BLOCKA | 0.8V supply to video codec |
BE14 | GND | GND |
BE15 | VDD_AO | 0.8V supply to AO digital core |
BE16 | VDD_AO | 0.8V supply to AO digital core |
BE17 | AO_MX41 | GPIO, I2C4 or SPI2 in AO domain |
BE18 | AO_MX42 | GPIO, I2C5 or PWM2 in AO domain |
BE19 | GND | GND |
BE20 | AO_MX43 | GPIO, I2C5 or PWM3 in AO domain |
BF1 | MIPI5_DP[3] | MIPI RX #5 |
BF2 | MIPI5_DN[3] | MIPI RX #5 |
BF3 | MIPI5_DP[1] | MIPI RX #5 |
BF4 | MIPI5_DN[1] | MIPI RX #5 |
BF6 | VDD_NPU_MEASURE | VDD_NPU for feedback |
BF7 | VDD_NPU | 0.8V supply to NPU |
BF8 | VDD_NPU | 0.8V supply to NPU |
BF9 | GND | GND |
BF10 | VDD | 0.8V supply to digital core |
BF11 | GND | GND |
BF12 | VDD_BLOCKA | 0.8V supply to video codec |
BF13 | VDD_BLOCKA | 0.8V supply to video codec |
BF14 | GND | GND |
BG6 | GND | GND |
BG7 | VDD_NPU | 0.8V supply to NPU |
BG8 | GND | GND |
BG9 | VDD | 0.8V supply to digital core |
BG10 | VDD | 0.8V supply to digital core |
BG11 | VDD_BLOCKA | 0.8V supply to video codec |
BG12 | VDD_BLOCKA | 0.8V supply to video codec |
BG13 | VDD_BLOCKA | 0.8V supply to video codec |
BG14 | VDD_BLOCKA | 0.8V supply to video codec |
BG15 | GND | GND |
BG16 | IV_MX2 | GPIO, Boot-configuration pin #2 |
BG17 | IV_MX1 | GPIO, Boot-configuration pin #1 |
BG18 | IV_MX3 | GPIO, Boot-configuration pin #3 |
BG19 | GND | GND |
BG20 | IV_MX5 | GPIO, Boot-configuration pin #5 |
BH1 | MIPI5_SN | MIPI RX #5 |
BH2 | MIPI5_SP | MIPI RX #5 |
BH3 | MIPI5_AVDD08 | 0.8V analog supply to MIPI #5 |
BH4 | MIPI5_AVSS | Analog GND to MIPI #5 |
BH6 | GND | GND |
BH7 | VDD_NPU | 0.8V supply to NPU |
BH8 | VDD_NPU | 0.8V supply to NPU |
BH9 | GND | GND |
BH10 | VDD | 0.8V supply to digital core |
BH11 | VDD | 0.8V supply to digital core |
BH12 | GND | GND |
BH13 | VDD_BLOCKA | 0.8V supply to video codec |
BH14 | VDD_BLOCKA | 0.8V supply to video codec |
BH15 | GND | GND |
BH16 | GND | GND |
BH17 | GND | GND |
BH18 | IV_MX6 | GPIO, Boot-configuration pin #6 |
BH19 | GND | GND |
BH20 | IV_MX4 | GPIO, Boot-configuration pin #4 |
BJ1 | MIPI5_DP[0] | MIPI RX #5 |
BJ2 | MIPI5_DN[0] | MIPI RX #5 |
BJ3 | MIPI5_AVDD18 | 1.8V analog supply to MIPI #5 |
BJ4 | MIPI5_AVSS | Analog GND to MIPI #5 |
BJ6 | GND | GND |
BJ7 | VDD_NPU | 0.8V supply to NPU |
BJ8 | VDD_NPU | 0.8V supply to NPU |
BJ9 | GND | GND |
BJ10 | VDD | 0.8V supply to digital core |
BJ11 | GND | GND |
BJ12 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BJ13 | GND | GND |
BJ14 | GND | GND |
BJ15 | GND | GND |
BJ16 | VDD_RTC | Connect to bypass capacitors |
BJ18 | CM4_PWR_EN | CM4 power enable |
BJ19 | CM4_WAKEUP_KEY | CM4 wake-up key (high active) |
BJ20 | IV_MX0 | GPIO, Boot-configuration pin #0 |
BK6 | GND | GND |
BK7 | VDD_NPU | 0.8V supply to NPU |
BK8 | VDD_NPU | 0.8V supply to NPU |
BK9 | GND | GND |
BK10 | VDD | 0.8V supply to digital core |
BK11 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BK12 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BK13 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BK14 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BK16 | VDDPST18_GPIO_RTC | 1.8V supply to RTC |
BK17 | RESET_B | Reset |
BK19 | X32K_AVSS | Analog GND to 32K crystal |
BK20 | X32K_AVDD18 | 1.8V analog supply to 32K crystal |
BL1 | MIPI5_DN[2] | MIPI RX #5 |
BL2 | MIPI5_DP[2] | MIPI RX #5 |
BL3 | MIPI5_AVSS | Analog GND to MIPI #5 |
BL5 | GND | GND |
BL6 | VDD | 0.8V supply to digital core |
BL7 | VDD | 0.8V supply to digital core |
BL8 | VDD | 0.8V supply to digital core |
BL9 | VDD | 0.8V supply to digital core |
BL10 | GND | GND |
BL11 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BL12 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BL13 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BL14 | VDD_CA55 | 0.7 ~ 1.0V supply to CA55 |
BL16 | GND | GND |
BL20 | SAR12B_AVDD18 | 1.8V analog supply to ADC |
BM1 | MIPI4_AVDD18 | 1.8V analog supply to MIPI #4 |
BM2 | MIPI4_AVDD08 | 0.8V analog supply to MIPI #4 |
BM3 | MIPI4_AVSS | Analog GND to MIPI #4 |
BM6 | GND | GND |
BM7 | GND | GND |
BM9 | GND | GND |
BM10 | GND | GND |
BM11 | GND | GND |
BM12 | GND | GND |
BM13 | GND | GND |
BM14 | GND | GND |
BM20 | SAR12B_AVSS | Analog GND to SAR ADC |
BN1 | USB3_VBUS | USB3 VBUS input |
BN2 | USB3_RESREF | USB3 reference resistor |
BN3 | USB3_DVDD08 | 0.8V supply to USB3 digital core |
BN4 | GND | GND |
BN7 | VDDPST18_GPIO_1 | 1.8V supply for GPIO 1 group |
BN9 | VDDPST18IO_SD | Connect to bypass capacitors |
BN10 | VDDPST18_SD | Connect to bypass capacitors |
BN12 | TML_AVDD18 | 1.8V analog supply for thermal sensor |
BN13 | VDDPST18_DVIO_1 | Connect to bypass capacitors |
BN15 | VDDPST18_DVIO_2 | Connect to bypass capacitors |
BN16 | GND | GND |
BN18 | AVSS_PLLS | Analog GND to PLLS |
BN19 | AVDD08_PLLS | 0.8V analog supply to PLLS |
BP1 | USB3_ID | USB3 |
BP2 | USB3_VDD33 | 3.3V supply to USB3 |
BP3 | USB3_AVDD08 | 0.8V analog supply to USB3 |
BP4 | GND | GND |
BP6 | G_MX12 | GPIO, Ethernet MAC SPI0 or I2C9 |
BP7 | G_MX5 | GPIO or Ethernet MAC |
BP9 | GND | GND |
BP10 | AVDDIO_3018_SD | 3.2V or 1.8V power output for SD card |
BP12 | VDDPST3018_DVIO_1 | 3.2V or 1.8V supply for DVIO_1 group |
BP13 | G_MX25 | GPIO or SPI NOR, SPI NAND or Parallel NAND |
BP15 | VDDPST3018_DVIO_2 | 3.2V or 1.8V supply for DVIO_2 group |
BP16 | VDDPST18_GPIO_0 | Connect to bypass capacitors |
BP18 | AVSS_PLLD | Analog GND to PLLD |
BP19 | AVDD08_PLLD | 0.8V analog supply to PLLD |
BR1 | USB20_AVDD18 | 1.8V analog supply to USB2 |
BR2 | USB20_AVDD33 | 3.3V analog supply to USB2 |
BR3 | GND | GND |
BR4 | GND | GND |
BR6 | G_MX11 | GPIO, Ethernet MAC SPI0 or I2C9 |
BR7 | G_MX6 | GPIO or Ethernet MAC |
BR9 | AVDDIO_3018_SDIO | 3.2V or 1.8V power output for SDIO |
BR10 | VDDPST18_SDIO | Connect to bypass capacitors |
BR12 | G_MX27 | GPIO or Parallel NAND |
BR13 | G_MX23 | GPIO, SPI NOR, SPI NAND or Parallel NAND |
BR15 | G_MX22 | GPIO, SPI NOR, SPI NAND or Parallel NAND |
BR16 | G_MX0 | GPIO or Ethernet MAC |
BR18 | AVSS_PLLC | Analog GND to PLLC |
BR19 | AVDD08_PLLC | 0.8V analog supply to PLLC |
BR20 | CPIOR-eCHRDY_I | CPIO |
BT1 | USB20_DP | USB2 |
BT2 | USB20_DM | USB2 |
BT3 | GND | GND |
BT4 | G_MX19 | GPIO or USB2 ID input |
BT6 | GND | GND |
BT7 | GND | GND |
BT9 | GND | GND |
BT10 | GND | GND |
BT12 | GND | GND |
BT13 | GND | GND |
BT15 | GND | GND |
BT16 | G_MX1 | GPIO or I2C6 |
BT18 | CPIOR_AVSS | Analog GND to CPIO |
BT19 | CPIOR_AVDD18 | 1.8V analog supply to CPIO |
BT20 | CPIOR-eRESET | CPIO |
BU1 | USB20_VBUS | USB2 |
BU2 | USB20_R_TEST | Leave open |
BU3 | GND | GND |
BU4 | G_MX18 | GPIO or USB2.0 DRV5ENB (low active) output |
BU6 | G_MX9 | GPIO, Ethernet MAC SPI0 or I2C8 |
BU7 | G_MX4 | GPIO, Ethernet MAC or I2C7 |
BU9 | AVDD30_SD_SDIO | 3.2V analog supply to SDIO |
BU10 | VDDPST18IO_SDIO | Connect to bypass capacitors |
BU12 | G_MX26 | GPIO, SPI-NOR, SPI-NAND or 8-bit NAND |
BU13 | G_MX24 | GPIO, SPI-NOR, SPI-NAND or 8-bit NAND |
BU15 | G_MX21 | GPIO, SPI-NOR, SPI-NAND or 8-bit NAND |
BU16 | G_MX2 | GPIO or I2C6 |
BU18 | CPIOR_AVSS | Analog GND to CPIO |
BU19 | CPIOR_AVDD08 | 0.8V analog supply to CPIO |
BU20 | CPIOR-eCHRDY_O | CPIO |
...
18.3.1 Data and Strobe Signals
| Ball Name | LPDDR4 | DDR4 | LPDDR3 | DDR3 |
|---|---|---|---|---|---|
DBYTE-0 | BP_D[0] | DQA0 | DQ0 | DQA0 | DQ0 |
BP_D[1] | DQA1 | DQ1 | DQA1 | DQ1 | |
BP_D[2] | DQA2 | DQ2 | DQA2 | DQ2 | |
BP_D[3] | DQA3 | DQ3 | DQA3 | DQ3 | |
BP_D[4] | DQA4 | DQ4 | DQA4 | DQ4 | |
BP_D[5] | DQA5 | DQ5 | DQA5 | DQ5 | |
BP_D[6] | DQA6 | DQ6 | DQA6 | DQ6 | |
BP_D[7] | DQA7 | DQ7 | DQA7 | DQ7 | |
BP_D[8] | DMA0/DBIA[0] | DM0/DBI[0] | DMA0 | DM0 | |
BP_D[9] | DQSA_T[0] | DQS_T[0] | DQSA_T[0] | DQS_T[0] | |
BP_D[10] | DQSA_C[0] | DQS_C[0] | DQSA_C[0] | DQS_C[0] | |
BP_D[11] |
|
|
|
| |
DBYTE-1 | BP_D[12] | DQA8 | DQ8 | DQA8 | DQ8 |
BP_D[13] | DQA9 | DQ9 | DQA9 | DQ9 | |
BP_D[14] | DQA10 | DQ10 | DQA10 | DQ10 | |
BP_D[15] | DQA11 | DQ11 | DQA11 | DQ11 | |
BP_D[16] | DQA12 | DQ12 | DQA12 | DQ12 | |
BP_D[17] | DQA13 | DQ13 | DQA13 | DQ13 | |
BP_D[18] | DQA14 | DQ14 | DQA14 | DQ14 | |
BP_D[19] | DQA15 | DQ15 | DQA15 | DQ15 | |
BP_D[20] | DMA1/DBIA[1] | DM1/DBI[1] | DMA1 | DM1 | |
BP_D[21] | DQSA_T[1] | DQS_T[1] | DQSA_T[1] | DQS_T[1] | |
BP_D[22] | DQSA_C[1] | DQS_C[1] | DQSA_C[1] | DQS_C[1] | |
BP_D[23] |
|
|
|
| |
DBYTE-2 | BP_D[24] | DQB0 | DQ16 | DQB0 | DQ16 |
BP_D[25] | DQB1 | DQ17 | DQB1 | DQ17 | |
BP_D[26] | DQB2 | DQ18 | DQB2 | DQ18 | |
BP_D[27] | DQB3 | DQ19 | DQB3 | DQ19 | |
BP_D[28] | DQB4 | DQ20 | DQB4 | DQ20 | |
BP_D[29] | DQB5 | DQ21 | DQB5 | DQ21 | |
BP_D[30] | DQB6 | DQ22 | DQB6 | DQ22 | |
BP_D[31] | DQB7 | DQ23 | DQB7 | DQ23 | |
BP_D[32] | DMB0/DBIB[0] | DM2/DBI[2] | DMB0 | DM2 | |
BP_D[33] | DQSB_T[0] | DQS_T[2] | DQSB_T[0] | DQS_T[2] | |
BP_D[34] | DQSB_C[0] | DQS_C[2] | DQSB_C[0] | DQS_C[2] | |
BP_D[35] |
|
|
|
| |
DBYTE-3 | BP_D[36] | DQB8 | DQ24 | DQB8 | DQ24 |
BP_D[37] | DQB9 | DQ25 | DQB9 | DQ25 | |
BP_D[38] | DQB10 | DQ26 | DQB10 | DQ26 | |
BP_D[39] | DQB11 | DQ27 | DQB11 | DQ27 | |
BP_D[40] | DQB12 | DQ28 | DQB12 | DQ28 | |
BP_D[41] | DQB13 | DQ29 | DQB13 | DQ29 | |
BP_D[42] | DQB14 | DQ30 | DQB14 | DQ30 | |
BP_D[43] | DQB15 | DQ31 | DQB15 | DQ31 | |
BP_D[44] | DMB1/DBIB[1] | DM3/DBI[3] | DMB1 | DM3 | |
BP_D[45] | DQSB_T[1] | DQS_T[3] | DQSB_T[1] | DQS_T[3] | |
BP_D[46] | DQSB_C[1] | DQS_C[3] | DQSB_C[1] | DQS_C[3] | |
BP_D[47] |
|
|
|
|
18.3.2 Address and Command
| Ball Name | LPDDR4 | DDR4 | LPDDR3 | DDR3 |
|---|---|---|---|---|---|
Master | BP_MEMRESET_L | RESET_N | RESET_N |
| RESET_N |
BP_ALERT_N |
| ALERT_N |
|
| |
ACX4-0 | BP_A[0] | CKEA0 | CKE0 | CKEA0 | CKE0 |
BP_A[1] | CKEA1 | CKE1 | CKEA1 | CKE1 | |
BP_A[2] | CSA0 | CS_N0 | CSA0 | CS_N0 | |
BP_A[3] | CSA1 | C0 | CSA1 |
| |
ACX4-1 | BP_A[4] | CLKA_T | BG0 | CLKA_T | BA2 |
BP_A[5] | CLKA_C | BG1 | CLKA_C | A14 | |
BP_A[6] |
| ACT_N |
| A15 | |
BP_A[7] |
| A9 |
| A9 | |
ACX4-2 | BP_A[8] | CAA0 | A12 | CAA0 | A12 |
BP_A[9] | CAA1 | A11 | CAA1 | A11 | |
BP_A[10] | CAA2 | A7 | CAA2 | A7 | |
BP_A[11] | CAA3 | A8 | CAA3 | A8 | |
ACX4-3 | BP_A[12] | CAA4 | A6 | CAA4 | A6 |
BP_A[13] | CAA5 | A5 | CAA5 | A5 | |
BP_A[14] |
| A4 | CAA6 | A4 | |
BP_A[15] |
| A3 | CAA7 | A3 | |
ACX4-4 | BP_A[16] |
| CLK0_T | CAA8 | CLK0_T |
BP_A[17] |
| CLK0_C | CAA9 | CLK0_C | |
BP_A[18] |
|
| ODTA |
| |
BP_A[19] |
|
|
|
| |
ACX4-5 | BP_A[20] | CKEB0 | CLK1_T | CKEB0 | CLK1_T |
BP_A[21] | CKEB1 | CLK1_C | CKEB1 | CLK1_C | |
BP_A[22] | CSB1 |
| CSB1 |
| |
BP_A[23] | CSB0 |
| CSB0 |
| |
ACX4-6 | BP_A[24] | CLKB_T | A2 | CLKB_T | A2 |
BP_A[25] | CLKB_C | A1 | CLKB_C | A1 | |
BP_A[26] |
| BA1 |
| BA1 | |
BP_A[27] |
| PAR |
| PAR | |
ACX4-7 | BP_A[28] | CAB0 | A13 | CAB0 | A13 |
BP_A[29] | CAB1 | BA0 | CAB1 | BA0 | |
BP_A[30] | CAB2 | A10 | CAB2 | A10 | |
BP_A[31] | CAB3 | A0 | CAB3 | A0 | |
ACX4-8 | BP_A[32] | CAB4 | C2 | CAB4 |
|
BP_A[33] | CAB5 | CAS_N | CAB5 | CAS_N | |
BP_A[34] |
| WE_N | CAB6 | WE_N | |
BP_A[35] |
| RAS_N | CAB7 | RAS_N | |
ACX4-9 | BP_A[36] |
| ODT0 | CAB8 | ODT0 |
BP_A[37] |
| ODT1 | CAB9 | ODT1 | |
BP_A[38] |
| CS_N1 | ODTB | CS_N1 | |
BP_A[39] |
| C1 |
|
|
...