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Case download:
uart_apb.zip

1 Design Brief

UART is short for Universal Asynchronous Receiver and Transmitter. Used for communication between serial input and serial output devices. Serial transmission comes at the cost of speed, in exchange for a reduction in cost and complexity of wiring. UART provides synchronization of serial asynchronous received data, parallel-to-serial and serial-to-parallel data conversion of the transmitter and receiver, for digital systems that need to convert serial data streams to parallel data, these functions Is essential. Synchronization of the serial data stream is achieved by adding start and stop bits to the transmitted data to form a data character. Data integrity is achieved by appending a parity bit to the data character, which is provided by the receiver Check this parity bit to check whether there is any transmission bit error. It is mainly composed of data bus interface, control logic, baud rate generator, sending part and receiving part.

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The UART controller IP core design is the AMBA APB slave bus interface, and our FBIO Wrapper is the AMBA AXI bus interface, which cannot be directly connected together, and requires an AXI2ABP Bridge to connect;

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We choose apb_ bus_ m32_bridge module from Bus Bridge series, it provides APB master bus interface to connect our IP,as shown in the figure below;

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This experiment uses the FPGA daughter board supporting the Plus1 7021 SP7021 SOC practice platform to complete the relevant experiment. The experiment is carried out in loopback mode, which is to connect the TX and RX of the UART controller IP core design; The development tool of FPGA daughter board uses XILINX's Vivado integrated development environment (version number is 2018.3); in order to facilitate the connection of the user's own verification IP to the SOC system for verification, this experiment provides the corresponding design reference basic files, as followsImage Removed

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The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the main board is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the main board and the FPGA Image Removed

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2: U20A on the motherboard is connected to J1 of the FPGA daughter board (Pin pins correspond to one, such as 1-1 ...), and the 42 pin IO (3.3v) of FPGA Bank 35 is extended via J17 for users to use

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6.2Implementation of System Software Platform for UART Controller IP Design Experiment Project

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Next, you need to copy all the files and folders under the installation directory \SP7021\example\uart_apb to the uart_apb project directory built above (the path is: installation directory \SP7021\workspace\uart_apb\), the file with the same name is selected to be overwritten, so that the UART The program codes main.c; uart.c; uart.h required for the IP design practice of the controller are placed in the following paths:

1） Install main.c in In the install directory \SP7021\workspace\uart_apb\main.c

2） Install uart.c in In the install directory \SP7021\workspace\uart_apb\testapi\util\uart.c

3） Install uart.h in the In the install directory \SP7021\workspace\uart_apb\include\util folder\uart.h

Finally, as shown in the figure below, the mouse selects the red box 1, then clicks the right mouse button to appear the drop-down menu, and then selects the red box 2, refresh the copy action just now, so that the file just copied can be displayed in the IDE environment

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main.c

int main(void)

{

    printf("Build @%s, %s\n", __DATE__, __TIME__);

    hw_init();

    sys_init();

    fbio_init();

    uart_ctl();

    disp_hdmi_init();

    uart_interrupt_init(); /*uart interrupt configure */

    sp_interrupt_setup(); /* system interrupt manager module init */

    printf("UART IP test ready ");

    while(1)

{

        unsigned int i;

        for (i = 0; i < 256; i++)

            {

               while   while(1)

                {

                   if   if((uart_reg->LSR&0x20)==0x20)

                  {

                     uart_reg->SER=0x3f;

                     uart_reg->TX_FIFO=i;

                     printf("@tx_data [%d]\n", i);

                     uart_reg->SER=0x3e;

                      break          break;

                   }

                }

            }

    }

}

对比数码管控制IP实验，增加了uartCompared with the digital tube control IP experiment, the uart_ctl () 函数，用来完成UART的配置及初始化操作，如下讲解。function is added to complete the configuration and initialization of the UART, as explained below.

void uart_ctl()

{

    uart_reg->LCR=0x20;

    printf("@LCR[%x]\n", temp);

    uart_reg->SER=0x3e;

    printf("@SER[%x]\n", temp);

    ///////////////// system clock is 65.057MHz//////65057000/16/buad//////

    uart_reg->BUAD_CNT=0x1A9; //9600

    printf("@BUAD_CNT[%x]\n", temp);

}

实现UART控制IP的配置及初始化操作,如下：

uartRealize the configuration and initialization operation of UART control IP as follows:

uart_reg->LCR=0x20;设置UART 为8bit 数据位，1bit 停止位，无校验位；

Set UART to 8bit data bit, 1bit stop bit, no parity bit;

uart_reg->SER=0x3e;设置UART 中断为：允许接收数据完成后产生中断；禁止发送数据完成后产生中断；禁止接收数据出现停止位，校验位错时产生中断；禁止接收数据FIFO满时产生中断；禁止发送数据FIFO空时产生中断；

Set the UART interrupt to: allow interrupts to be generated after receiving data is complete; disable interrupts to be generated after data transmission is complete; prohibit stop bits from receiving data and generate interrupts when the check bit is wrong; disable interrupts when receiving data FIFO is full; Generate an interrupt;

uart_reg->BUAD_CNT=0x1A9;

设置UART 波特率为9600Set the UART baud rate to 9600;

下面介绍The following introduces while (1) loop

if((uart_reg->LSR&0x20)==0x20) : 判断接收数据FIFO为空Judge that the received data FIFO is empty

uart_reg->SER=0x3f; Forbid receiving data interruption; 禁止接收数据中断；

uart_reg->TX_FIFO=i; 将数据i送到TX Send data i to TX FIFO;

uart_reg->SER=0x3e;  允许接收数据完成后产生中断  Allow interrupt generation after receiving data

uart.c

#include "common_all.h"

#include "cache.h"

#include "sp_interrupt.h"

#define FPGA_EXT0_INT  (29)

#define FPGA_EXT1_INT  (30)

static unsigned int g_repeat_cnt = 0;

unsigned int rx_data;

void fpga_ext0_interrupt_control_mask(int enable)

void fpga_ext1_interrupt_control_mask(int enable)

static void fpga_ext0_isr_cfg()

static void fpga_ext1_isr_cfg()

void fpga_ext0_callback(void)

void fpga_ext1_callback(void)

void uart_interrupt_init ()

void fpga_ext1_test_init()

对比数码管控制IP实验的led.c，结构类似，不同的是中断处理程序不同，如下讲解Compared with the LED.c of the LED control IP experiment, the structure is similar, the difference is that the interrupt handler is different, as explained below

void fpga_ext0_callback(void)

{

    rx_data=uart_reg->RX_FIFO;

    printf("@rx_data [%d]\n", rx_data);

    uart_reg->LSR=0x0;

}此中断处理程序的作用：将RX FIFO收到的8bit数据取出；然后清除本次中断的状态标识bit，这样就完成了1byte数据的串行接收和发送实验。

The role of this interrupt handler: take the 8bit data received by the RX FIFO; then clear the status flag bit of this interrupt, so that the serial reception and transmission experiments of 1byte data are completed.

uart.h

#ifndef __FPGAINT_H__

#define __FPGAINT_H__

#define  #define  FBIO_BASE_ADDR 0x70000000

typedef struct uart_reg_s {

    unsigned long LCR;

    unsigned long SER;

    unsigned long BUAD_CNT;

    unsigned long LSR;

    unsigned long RX_FIFO;

    unsigned long TX_FIFO;

} uart_reg_t;

extern uart_reg_t *uart_reg;

void uart_interrupt_init ();

void fpga_ext1_test_init();

#endif // __FPGAINT_H__

定义了UART控制IP相关寄存器

程序代码运行

在Plus1 IDE环境中compile后，下载到平台，在terminal窗口看到如下信息Defined UART control IP related registers

6.3 Run Program code

After compile in the Plus1 IDE environment, download to the platform and see the following information in the terminal window

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