This document elucidates the application circuits associated with the SP7350. It serves as a supplementary resource to the specification of the SP7350.
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Operating on a mere 1.8 volts, the RTC module is notably efficient. Its internal Low Dropout Regulator (LDO) generates a 0.8-volt power supply specifically for the RTC digital core. Refer to the schematic below for recommended power pin configurations, which necessitate the inclusion of bypass capacitors on the X32K_AVDD18, VDDPST18_GPIO_RTC and VDD_RTC pins.
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The schematic below illustrates a sample RTC_1V8 power supply circuit using that uses a super capacitor . It draws for backup power.. The circuit draws primary power from the 5V VCC source and uses a 0.47 Farad super capacitor to store energy and maintain power to the RTC during VCC interruptions in the main supply. Resistor R16 (470Ω) limits the capacitor's charging current, while diode D3 blocks reverse current flow, preventing the super capacitor from discharging back into the VCC line when the external power is unavailable. A low quiescent current 1.8V LDO regulator converts VCC_RTC to the required 1.8V (RTC_1V8) needed for RTC module operation.
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The schematic below illustrates a sample RTC_1V8 power supply circuit using that uses a Lithium battery for backup power. When external power is presentavailable, the circuit draws power from the 5V VCC source. When the external source is unavailable, it automatically switches to draw power from the Lithium battery (B1). Diode D3 blocks reverse current flow, preventing the Lithium battery from feeding back into the VCC supply when external source is unavailable. Diode D4 prevents charging current from flowing into the Lithium battery when VCC is present. A low quiescent current 1.8V LDO regulator converts VCC_RTC to the necessary 1.8V (RTC_1V8) required by the RTC module.
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All power sources should be managed using the CM4_PWR_EN signal. Specifically, when CM4_PWR_EN is set to LOW, all power supplies, including those for the CM4 and Main power domain, should be deactivated.
Please refer to the provided power scheme for details on power control.
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Refer to the power scheme illustrated below. All powers in the main power domain should be controlled by both CM4_PWR_EN and MAIN_PWR_EN signals. Specifically, all powers in the main power domain are only turned on when both CM4_PWR_EN and MAIN_PWR_EN are set to HIGH.
It's important to note that during cold booting, CM4_PWR_EN goest to HIGH to initiate the booting process. Therefore, the default state ofMAIN_PWR_EN (when the GPIO is not yet programmed) should be HIGH to allow the CA55 to start booting.
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Typically, MAIN_PWR_EN is controlled by a GPIO in the CM4 domain. CM4 can directly set the power of the main power domain to either on or off.
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DDR Type | Max. Clock | Max. Data Rate | Max. BW (16 bits) | Max. BW (32 bits) |
|---|---|---|---|---|
LPDDR4 | 1.600 GHz | 3200 MT/s | 6.4 GB/s | 12.8 GB/s |
DDR4 | 1.333 GHz | 2666 MT/s | 5.3 GB/s | 10.7 GB/s |
LPDDR3 / DDR3 / DDR3L | 0.933 MHz | 1866 MT/s | 3.7 GB/s | 7.5 GB/s |
Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.
5.1 Data Bus and Data Strobe Signals Wiring
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The SP7350 supports SPI-NAND flash for booting. To boot from an SPI-NAND flash, set the bootstrap pins IV_MX[6:2] to [1 1 1 0 1]. The SP7350 supports either 2k-sector with 1 or 2 planes or 4k-sector with 1 plane. When using a 1.8V flash chip, the maximum clock frequency is 153 MHz. It's advisable to use a 1.8V flash chip for optimal high-speed operation.
Special Note:
NAND flash memory in the market is categorized into SLC (Single-Level Cell) and MLC (Multi-Level Cell) types. MLC NAND has a higher likelihood of developing bad cells. It's important to note that the Linux ubifs (sorted block image file system) subsystem does not support MLC NAND. Therefore, if you plan to use NAND flash as the primary storage (boot) device, it is recommended to opt for SLC NAND flash.
10.1 SPI-NAND Interface of SP7350
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The SP7350 supports booting from 8-bit NAND flash. To boot from an 8-bit NAND flash, set the bootstrap pins IV_MX[6:2] to [1 0 0 0 1]. The SP7350 is compatible with 2k-sector, 4k-sector, or 8k-sector NAND flash. For optimal high-speed performance, it's recommended to use a 1.8V VCCQ power supply.
Special Note:
NAND flash memory in the market is categorized into SLC (Single-Level Cell) and MLC (Multi-Level Cell) types. MLC NAND has a higher likelihood of developing bad cells. It's important to note that the Linux ubifs (sorted block image file system) subsystem does not support MLC NAND. Therefore, if you plan to use NAND flash as the primary storage (boot) device, it is recommended to opt for SLC NAND flash.
11.1 8-bit NAND Interface of SP7350
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ILIM = 6800/6800 = 1.0 (A)
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Note that R218 and C247 are requested and defined by OTG specification. Do not alter their values.
The UPHY0_DRV5V_ENB signal (GPIO18) controls VBUS on/off states, generated by the OTG hardware of SP7350.
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ILIM = 6800/6800 = 1.0 (A)
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Note that R10 and C198 are requested and defined by OTG specification. Do not alter their values.
The UPHY0_DRV5V_ENB signal (GPIO18 of SP7350) controls VBUS on/off states, generated by the OTG hardware of SP7350.
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17.2 MIPI-RX2 and MIPI-RX3
Note that MIPI-RX2 is not available for version A chips.
When CPIO is disabled, MIPI-RX2 and MIPI-RX3 are available for use. MIPI-RX2 supports four data and one clock lanes (4d1c) with 4 virtual channels if MIPI-RX3 is not enabled. However, if MIPI-RX3 is enabled, both MIPI-RX2 and RX3 support two data and one clock lanes (2d1c). Each data lane can transmit up to 1.5 Gbps. Please refer to the table for pin sharing between MIPI-RX2, MIPI-RX3, and CPIO.
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