The Input Capture Module (ICM) is used to capture a counter value from the ICM's internal counter based upon an event on an input pin. There are four ICM sub modules in the SP7021. The ICM's input source can come from external pins or internal test signal, the counter clock source can also come from external clocks or internal system clock. The ICM features are useful in applications that require frequency (time period) and pulse measurement. The ICM control registers locate at RGST table Group 81.0~31 which memory map in 0x9C002880~0x9C0028FF.
The detail ICM features of the sub module are as below.
Below description will focus on ICM0 , the ICM1/2/3 have the same structure and correspond registers.
11.2 Function Diagram
A generalized function diagram of ICM is shown in Figure 1011-1.
Figure 1011-1 ICM Function Blocks
- I_Mux_5T1: 4 external input signals and 1 internal test signal. Test signal generate from system clock and support to scale the period.
- I_DEBOUNCE_FILTER: Used to filter out noise.
- I_EDGE_EVENT: Three operating modes and all of them can be set event times that decide when to trigger interrupt.
- Rising Edge Detect Mode
- Falling Edge Detect Mode
- Edge Detect Mode
11.3 Input Source and Clock
There are 4 input pins and 1 test signal can be selected as input signal source by icm0_mux_sel in ICM0. The icm0_mux_sel is in bit[5:3] of RGST table Group 81.0 icm0_cfg0 register. The ICM0's count clock can be selected by icm0_clk_sel. 4 external clock come from input pins and others source are SYSCLK, 27MHz and 32KHz. The icm0_clk_sel is in bit[8:6] of RGST table Group 81.0 icm0_cfg0 register.
11.4 Input Capture Detect Mode
The input capture detect mode of ICM0 can be selected by icm0_ee_mode. The icm0_ee_mode is in bit[1:0] of RGST table Group 81.1 icm0_cfg1 register. Set icm0_ee_mode as 0 for Rising Edge Mode, set icm0_ee_mode as 1 for Falling Edge Mode and set icm0_ee_mode as 2 for Edge Detection Mode. The interrupt trigger timing is controlled by icm0_ee_times. If icm0_ee_times set 7, the interrupt will be triggered after 7 times edge event. The icm0_ee_ times is in bit[5:2] of RGST table Group 81.1 icm0_cfg1 register.
11.4.1 Rising Edge Mode
Figure 1011-2 shows the icmx_ee_mode = 0 and icmx_ee_times = 0 or 1 case.
Figure 1011-2 Rising Edge Mode Case1
Figure 1011-3 shows the icmx_ee_mode = 0 and icmx_ee_times = 3 case.
Figure 1011-3 Rising Edge Mode Case2
11.4.2 Falling Edge Mode
Figure 1011-4 shows the icmx_ee_mode = 1 and icmx_ee_times = 0 or 1 case.
Figure 1011-4 Falling Edge Mode Case1
Figure 1011-5 shows the icmx_ee_mode = 1 and icmx_ee_times = 2 case.
Figure 1011-5 Falling Edge Mode Case2
11.4.3 Edge Detection Mode
Figure 1011-6 shows the icmx_ee_mode = 2 and icmx_ee_times = 0 or 1 case.
Figure 1011-6 Edge Detection Mode Case1
Figure 1811-7 shows the icmx_ee_mode = 2 and icmx_ee_times = 2 case.
Figure 1011-7 Edge Detection Mode Case2
11.5 Interrupt Trigger Counter
The ICM0 interrupt trigger counter value control register is RGST table Group 81.4 icm0_cnt. This register will record the counter value when interrupt happened. This value is updated from FIFO, the FIFO depth is 16. Figure 1011-8 shows the behavior of counter. When interrupt trigger at internal counter 9, the icm0_cnt will be updated to 9 immediately.
Figure 1011-8 counter behavior
11.6 Debounce Filter
The ICM0 debounce filter is controled by icm0_df_times which is bit[8:6] of Group81.1 icm0_cfg1 register. Set the debounce times as 7, the input signals length under 7 clock will be filtered. Figure 1011-9 shows the icm0_df_times=4 case.
Figure 1011-9 icm0_df_times=4 case
11.7 Count Pulse Width H and L
The ICM0 pulse width H and L count value will be recorded in Group 81.5 icm0_pulse_width_h and Group 81.6 icm0_pulse_width_l registers. Figure 1011-10 shows the count pulse width H and L status.
Figure 1011-10 Count Pulse Width H and L
11.8 Registers Map
11.8.1 Registers Memory Map
ICM0 Config Register 0
ICM0 Config Register 1
ICM0 Internal Counter Scaler
ICM0 Interrupt Trigger Counter Value
ICM0 Pulse Width H
ICM0 Pulse Width L
ICM1 Config Register 0
ICM1 Config Register 1
ICM1 Internal Counter Scaler
ICM1 Interrupt Trigger Counter Value
ICM1 Pulse Width H
ICM1 Pulse Width L
ICM2 Config Register 0
ICM2 Config Register 1
ICM2 Internal Counter Scaler
ICM2 Interrupt Trigger Counter Value
ICM2 Pulse Width H
ICM2 Pulse Width L
ICM3 Config Register 0
ICM3 Config Register 1
ICM3 Internal Counter Scaler
ICM3 Interrupt Trigger Counter Value
ICM3 Pulse Width H
ICM3 Pulse Width L
11.8.2 Registers Description
RGST Table Group 81 ICM
81.0 ICM0 Config Register 0 (icm0 cfg0)
Reset: 0x0000 0000