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For command ring, the HW will implement an internal Current Cycle State(CCS). The ring is empty when CCS != TRB.C. The initial value of CCS is RCS in CRCR register. When ever a link TRB with TC TC bit set is read in, the CCS toggles. For event ring, this bit is always 0.
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The event ring will be full if HW has and TRB to write and the next TRB address reaches the de-queue pointer. For command ring, the SW can read the CRCR register for the current TRB address which which HW is process.
- Command Ring Size
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