...
Address | Group No. | Register Name | Description |
|---|---|---|---|
0x9C002880 | G81.0 | icm0_cfg0 | ICM0 Config Register 0 |
0x9C002884 | G81.1 | icm0_cfg1 | ICM0 Config Register 1 |
0x9C002888 | G81.2 | icm0_cfg2 | ICM0 Internal Counter Scaler |
0x9C00288C | G81.3 | icm0_cfg3 | ICM0 Test Signal Scaler |
0x9C002890 | G81.4 | icm0_cnt | ICM0 Interrupt Trigger Counter Value |
0x9C0028900x9C002894 | G81.45 | icm0_pulse_witdhwidth_h | ICM0 Pulse Width H |
0x9C0028940x9C002898 | G81.56 | icm0_pulse_width_l | ICM0 Pulse Width L |
0x9C0028980x9C00289C | G81.67 | icm1_cfg0 | ICM1 Config Register 0 |
0x9C00289C0x9C0028A0 | G81.78 | icm1_cfg1 | ICM1 Config Register 1 |
0x9C0028A00x9C0028A4 | G81.89 | icm1_cfg2 | ICM1 Internal Counter Scaler |
0x9C0028A8 | G81.10 | icm1_cfg3 | ICM1 Test Signal Scaler |
0x9C0028A40x9C0028AC | G81.911 | icm1_cnt | ICM1 Interrupt Trigger Counter Value |
0x9C0028A80x9C0028B0 | G81.1012 | icm1_pulse_witdh_h | ICM1 Pulse Width H |
0x9C0028AC0x9C0028B4 | G81.1113 | icm1_pulse_width_l | ICM1 Pulse Width L |
0x9C0028B00x9C0028B8 | G81.1214 | icm2_cfg0 | ICM2 Config Register 0 |
0x9C0028B40x9C0028BC | G81.1315 | icm2_cfg1 | ICM2 Config Register 1 |
0x9C0028B80x9C0028C0 | G81.1416 | icm2_cfg2 | ICM2 Internal Counter Scaler |
0x9C0028BC0x9C0028C4 | G81.1517 | icm2_cfg3 | ICM2 Test Signal Scaler |
0x9C0028C8 | G81.18 | icm2_cnt | ICM2 Interrupt Trigger Counter Value |
0x9C0028C00x9C0028CC | G81.1619 | icm2_pulse_witdh_h | ICM2 Pulse Width H |
0x9C0028C40x9C0028D0 | G81.1720 | icm2_pulse_width_l | ICM2 Pulse Width L |
0x9C0028C80x9C0028D4 | G81.1821 | icm3_cfg0 | ICM3 Config Register 0 |
0x9C0028CC0x9C0028D8 | G81.1922 | icm3_cfg1 | ICM3 Config Register 1 |
0x9C0028D00x9C0028DC | G81.2023 | icm3_cfg2 | ICM3 Internal Counter Scaler |
0x9C0028E0 | G81.24 | icm3_cfg3 | ICM3 Test Signal Scaler |
0x9C0028D40x9C0028E4 | G81.2125 | icm3_cnt | ICM3 Interrupt Trigger Counter Value |
0x9C0028D80x9C0028E8 | G81.2226 | icm3_pulse_witdh_h | ICM3 Pulse Width H |
0x9C0028DC0x9C0028EC | G81.2327 | icm3_pulse_width_l | ICM3 Pulse Width L |
0x9C0028E00x9C0028F0 | G81.2428 | reserved | reserved |
0x9C0028E40x9C0028F4 | G81.2529 | reserved | reserved |
0x9C0028E80x9C0028F8 | G81.2630 | reserved | reserved |
0x9C0028EC | G81.27 | reserved | reserved |
0x9C0028F0 | G81.28 | reserved | reserved |
0x9C0028F4 | G81.29 | reserved | reserved |
0x9C0028F8 | G81.30 | reserved | reserved |
0x9C0028FC | G81.31 | reserved | reserved |
...
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Example, Intend bit 1 = 1. Set this register : If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit). (Example 敘述看不懂) |
| Reserve | 15:9 | RO | |
| icm0 clk sel | 8:6 | RW | ICM0 Clock Source Select (Default value 是哪一個 ? 麻煩在後方註明 (Default)) |
| icm0 mux sel | 5:3 | RW | Select input signal source. 在 7021, 接到 Input 0/1/2/3 的各是什麼信號 ? |
| icm0 int clr | 2 | RWW1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | Reserved |
| icm0 en | 0 | RW | Input Capture Module 0 Enable 2. Clear the inter- rupt. (2 這句是什麼意思?)ICM0 enable When set this bit to 0, it mean disabled input capture module 0 and the interrupt also cleared. |
81.1 ICM0 Config Register 1 (icm0 cfg1)
Address: 0x9C002884
Reset: 0x0000 4000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Example, Intend bit 1 = 1. Set this register : If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit). (Example 敘述看不懂) |
| icm0 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0x00: Non-full 0x11: Full |
| icm0 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0x00: Non-Empty 0x11: Empty |
| icm0 fifo clr | 13 | RWW1C | Input Capture Module 0 FIFO Clear 0x00: Writing 0 to this bit has no effect 0x11: Clear fifo and icm fifo data drop. (表示 bit 12 會 report status 嗎?)有關 Clear 相關的信號, 都要敘述會自行回復 0, 還是軟體要自己寫 0 回復. 如果會自己回復 0, 那這個bit attribute 是 W1C (Write 1 Clear) 而不是 RW Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm0 fifo data drop | 12 | RO | Input Capture Module 0 Data Dropped 0x00: Non-dropped 0x11: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | Reserved |
| icm0 df times | 8:6 | RW | Input Capture Module 0 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal de- bounce debounce filter. 0 0x0-6: icm0 df times+1 times, 7 0x7: 16 times描述看不懂設定如何對應 debounce 時間, 是 0x0 表示沒有, 0x7 表示敲過7次嗎 ? |
| icm0 ee times | 5:2 | RW | 信號全名 ?Input capture module interrupt trigger threshold Set 0-15. If set 7, intterrupt interrupt will be triggered after 8 times edge event. 看不懂敘述 |
| icm0 ee mode | 1:0 | RW | Input capture detect mode Select Others : ? (沒有敘述)don't care. |
81.2 ICM0 Internal Counter Scaler (icm0 cfg2)
Address: 0x9C002888
Reset: 0x0000 0000
| Field Name | Bit | Access | Description | ||
| icm0 cnt scale | 31:0 | RW | RW | ICM0 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1 ) On clk cnt rising edge, (internalcounter) = (internal counter ) + 1 |
81.3 ICM0 Test Signal Scaler (icm0 cfg3)
Address: 0x9C00288C
...
| Field Name | Bit | Access | Description |
| icm0 test sig scale | 31:0 | RW | 信號全名 ?ICM0 Test Signal Scaler Test signal prescaler 0-(2ˆ32-1). clk test = sysclk / (icmx test sig scale+1) On clk test rising edge, system will generat generate 1T pulse signal. The Test Signal Period = (icm0 test sig scale+1) + 1, UNIT : T(sysclk) 敘述看不懂 |
81.4 ICM0 Interrupt Trigger Counter Value (icm0 cnt)
Address: 0x9C002890
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm0 cnt | 31:0 | RO | 信號全名 ?ICM0 Interrupt Trigger Counter Value Record the internal counter value when interrupt happen. Read this from fifo (depth is 15).意思是說作為 interrupt 發生次數的 counter 嗎 ? 後面那句 read this from FIFO 是什麼意思 ?happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
81.5 ICM0 Pulse Width H (icm0 pulse witdh h)
Address: 0x9C002894
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm0 pulse width h | 31:0 | RO | 信號全名 ? Pulse width : high ICM0 Pulse Width H Square pulse high level width (unit : t ext clk)指的是 Positive Pulse 發生次數嗎 ? |
81.6 ICM0 Pulse Width L (icm0 pulse width l)
Address: 0x9C002898
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm0 pulse width l | 31:0 | RO | 信號全名 ? Pulse width : low ICM0 Pulse Width L Square pulse low level width (unit : t ext clk)指的是 Negative Pulse 發生次數嗎 ? |
ICM1 ~ 3 register 的問題與 ICM0 同
81.7 ICM1 Config Register 0 (icm1 cfg0)
Address: 0x9C00289C
...
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Example , Intend bit 1 = 1. Set this register: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit). |
| Reserve | 15:9 | RO | |
| icm1 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm1 mux sel | 5:3 | RW | Select input signal source. 0: Input 0 1: Input 1 2: Input 2 3: Input 3 4: Test Signal Others: 0 |
| icm1 int clr | 2 | RWW1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | |
| icm1 en | 0 | RW | 1. Disable the input capture module. 2. Clear the interrupt.ICM1 enable When set this bit to 0, it mean disabled input capture module 1 and the interrupt also cleared. |
81.8 ICM1 Config Register 1 (icm1 cfg1)
Address: 0x9C0028A0
Reset: 0x0000 4000
...
| Field Name | Bit | Access | Description | ||
| Write Mask Bits | 31:16 | RW | Write Mask Bits Example , Intend bit 1 = 1. Set this register: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit). | ||
| icm1 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full | ||
| icm1 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-mptyEmpty 1: Empty | ||
| icm1 fifo clr | 13 | RW | Clear | W1C | Input Capture Module 1 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm1 fifo data drop | 12 | RO | Input Capture Module 1 Data Dropped 0: Non-dropped 1: Indicate the fifo data | dropeddropped. | |
| Reserve | 11:9 | RORO | Reserved | ||
| icm1 df times | 8:6 | RW | Input Capture Module 1 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal de- bouncedebounce filter. 00x0-6: icm0icm1 df times+1 times, 70x7: 16 times | ||
| icm1 icm10 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, intterruptinterrupt will be triggered after 8 times edge event. | ||
| icm1 ee mode | 1:0 | RW | Select the input Input capture detect mode .Select 0x0: Rising Edge Mode 0x1: Falling Edge Mode 0x2: Edge Detection Mode Others don't care. |
81.9 ICM1 Internal Counter Scaler (icm1 cfg2)
Address: 0x9C0028A4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 cnt scale | 31:0 | RW | ICM1 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) On clk cnt rising edge, (internal counter) = (internal counter) + 1(icmx cnt scale+1) |
81.10 ICM1 Test Signal Scaler (icm1 cfg3)
Address: 0x9C0028A8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 test sig scale | 31:0 | RW | ICM1 Test Signal Scaler Test signal prescaler 0-(2ˆ32-1). clk test = sysclk / (icmx test sig scale+1) On clk test rising edge, system will generat generate 1T pulse signal. The Test Signal Period = (icm0 test sig scale+1) + 1, UNIT : T(sysclk) |
81.11 ICM1 Interrupt Trigger Counter Value (icm1 cnt)
Address: 0x9C0028AC
...
| Field Name | Bit | Access | Description |
| icm1 cnt | 31:0 | RO | ICM1 Interrupt Trigger Counter Value Record the internal counter value when interrupt happen. Read this from fifo (depth is 15)happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
81.12 ICM1 Pulse Width H (icm1 pulse witdh h)
Address: 0x9C0028B0
Reset: 0x0000 0000
...
| Field Name | Bit | Access | Description |
| icm1 pulse width h | 31:0 | RO | ICM1 Pulse width : highWidth H Square PWM pulse high level width (unit : t ext clk) |
81.13 ICM1 Pulse Width L (icm1 pulse width l)
Address: 0x9C0028B4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 pulse width l | 31:0 | RO | ICM1 Pulse width : lowWidth L Square PWM pulse low level width (unit : t ext clk) |
81.14 ICM2 Config Register 0 (icm2 cfg0)
Address: 0x9C0028B8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RWRW | Write Mask Bits Example , Intend bit 1 = 1. Set this register: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit). |
| Reserve | 15:9 | RO | |
| icm2 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm2 mux sel | 5:3 | RW | Selec input signal source. 0: Input 0 1: Input 1 2: Input 2 3: Input 3 4: Test Signal Others: 0 |
| icm2 int clr | 2 | RWW1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | |
| icm2 en | 0 | RW | ICM2 enable 0: Disable (default), interrupt also cleared When set this bit to 0, it mean disabled input capture module .2 . Clear the inter- rupt.0: Disable (default) 1: Enable and the interrupt also cleared. |
81.15 ICM2 Config Register 1 (icm2 cfg1)
Address: 0x9C0028BC
...
| Field Name | Bit | Access | Description | ||||
| Write Mask Bits | 31:16 | RW | Write Mask Bits Example | , Intend bit 1 = 1. Set this register : If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit). | |||
| icm2 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full | ||||
| icm2 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non- | mptyEmpty 1: Empty | |||
| icm2 fifo clr | 13 | RW | Clear fifoW1C | Input Capture Module 2 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. | |||
| icm2 fifo data drop | 12 | ROClear | fifo and icm fifo data drop Input Capture Module 2 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. | ||||
| Reserve | 11:9 | RO | Reserved | ||||
| icm2 df times | 8:6 | RW | Input Capture Module 2 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal de- bouncedebounce filter. 00x0-6: icm0icm2 df times+1 times, 70x7: 16 times | ||||
| icm2 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, | intterrupt interrupt will be triggered after 8 times edge event. | |||
| icm2 ee mode | 1:0 | RW | Select the inputInput capture detect mode | .Select | 00x0: Rising Edge Mode | 10x1: Falling Edge Mode | 20x2: Edge Detection Mode Others don't care. |
81.16 ICM2 Internal Counter Scaler (icm2 cfg2)
Address: 0x9C0028C0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 cnt scale | 31:0 | RW | ICM2 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1 ) On clk cnt rising edge, (internal counter) = (internal counter) + 1 |
81.17 ICM2 Test Signal Scaler (icm2 cfg3)
Address: 0x9C0028C4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 test sig scale | 31:0 | RW | ICM2 Test Signal Scaler Test signal prescaler 0-(2ˆ32-1). clk test = sysclk / (icmx test sig scale+1) On clk test rising edge, system will generat generate 1T pulse signal. The Test Signal Period = (icm0 test sig scale+1) + 1, UNIT : T(sysclk) |
81.18 ICM2 Interrupt Trigger Counter Value (icm2 cnt)
Address: 0x9C0028C8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 cnt | 31:0 | RO | ICM2 Interrupt Trigger Counter Value Record the internal counter value when interrupt happen. Readthis from fifo (depth is 15) happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
81.19 ICM2 Pulse Width H (icm2 pulse witdh h)
Address: 0x9C0028CC
...
| Field Name | Bit | Access | Description |
| icm2 pulse width h | 31:0 | RO | ICM2 Pulse width : highWidth H Square PWM pulse high level width (unit : t ext clk) |
81.20 ICM2 Pulse Width L (icm2 pulse width l)
Address: 0x9C0028D0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 pulse width l | 31:0 | RO | ICM2 Pulse width : lowWidth L Square PWM pulse low level width (unit : t ext clk) |
81.21 ICM3 Config Register 0 (icm3 cfg0)
Address: 0x9C0028D4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Example , Intend bit 1 = 1. Set this register: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit). |
| Reserve | 15:9 | RO | |
| icm3 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm3 mux sel | 5:3 | RW | Select input signal source. 0: Input 0 1: Input 1 2: Input 2 3: Input 3 4: Test Signal Others: 0 |
| icm3 int clr | 2 | RWW1C | Clear the interrupt. 1: Clear Interrupt ) Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | |
| icm3 en | 0 | RW | 1. Disable the input capture module. 2. Clear the inter- rupt. ICM3 enable When set this bit to 0, it mean disabled input capture module 3 and the interrupt also cleared. |
81.22 ICM3 Config Register 1 (icm3 cfg1)
Address: 0x9C0028D8
Reset: 0x0000 4000
...
| Field Name | Bit | Access | Description | ||||
| Write Mask Bits | 31:16 | RW | Write Mask Bits Example | , Intend bit 1 = 1. Set this register : If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit). | |||
| icm3 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full | ||||
| icm3 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non- | mptyEmpty 1: Empty | |||
| icm3 fifo clr | 13 | RW | Clear | W1C | Input Capture Module 3 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. | ||
| icm3 fifo data drop | 12 | RO | Input Capture Module 3 Data Dropped 0: Non-dropped 1: Indicate the fifo data | dropeddropped. | |||
| Reserve | 11:9 | RO | Reserved | ||||
| icm3 df times | 8:6 | RW | Input Capture Module 3 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal | de- bounce debounce filter. | 00x0-6: | icm0 icm3 df times+1 times, | 70x7: 16 times |
| icm3 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, | intterrupt interrupt will be triggered after 8 times edge event. | |||
| icm3 ee mode | 1:0 | RW | Select the inputInput capture detect mode | .Select | 00x0: Rising Edge Mode | 10x1: Falling Edge Mode | 20x2: Edge Detection Mode Others don't care. |
81.23 ICM3 Internal Counter Scaler (icm3 cfg2)
Address: 0x9C0028DC
...
| Field Name | Bit | Access | Description |
| icm3 cnt scale | 31:0 | RW | ICM3 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) On clk cnt rising edge, (internal counter) = (internal counter) + 1clk cnt = ext clk / (icmx cnt scale+1) |
81.24 ICM3 Test Signal Scaler (icm3 cfg3)
Address: 0x9C0028E0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm3 test sig scale | 31:0 | RW | ICM3 Test Signal Scaler Test signal prescaler 0-(2ˆ32-1). clk test = sysclk / (icmx test sig scale+1) On clk test rising edge, system will generat generate 1T pulse signal. The Test Signal Period = (icm0 test sig scale+1) + 1, UNIT : T(sysclk) |
81.25 ICM3 Interrupt Trigger Counter Value (icm3 cnt)
Address: 0x9C0028E4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm3 cnt | 31:0 | RO | ICM3 Interrupt Trigger Counter Value Record the internal counter value when interrupt happen. Read this from fifo (depth is 15)happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
81.26 ICM3 Pulse Width H (icm3 pulse witdh h)
Address: 0x9C0028E8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm3 pulse width h | 31:0 | RO | ICM3 Pulse width : highWidth H Square PWM pulse high level width (unit : t ext clk) |
81.27 ICM3 Pulse Width L (icm3 pulse width l)
Address: 0x9C0028EC
...
Field Name | Bit | Access | Description |
icm3 pulse width l | 31:0 | RO | ICM3 Pulse width : low Width L Square PWM pulse low level width (unit : t ext clk) |
81.28 (Reserved)
Address: 0x9C0028F0
Reset: 0x0000 0000
...