Under construction…
A built-in ROM code.
Load x-boot image from a boot storage device into SRAM and run it.
Support 6 boot storage devices:
SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card
USB2.0 and USB3.0 flash drives
Support secure-boot.
Support encrypted x-boot.
CPU core 0 is the boot-core and is responsible for booting.
CPU core 1, 2 and 3 spin at i-boot until being waked up.
Support warm-boot (wake up from deep-sleep mode).
CPU core 0 is the boot core.
CPU core 0 is responsible for all boot processes from i-boot to Linux.
CPU core 1, 2 and 3 spin (enter wfe mode) after initialize itself at i-boot.
Run Control of CPU Pen (at bootcompat session) :
CPU_WAIT_INIT_VAL (0xffffffff) // CPU waiting (spinning)
CPU_WAIT_A64_VAL (0xfffffffe) // CPU goes to A64
x (address other than above) // CPU goes to x
Bootstrap pins of SP7350
State of bootstrap pins of SP7350 will be read into bootstrap register (G0.31) at the moment that power-on reset is released. Refer to definition of boot-strap pins of SP7350 below:
Boot-strap pins of SP7350 | Boot devices | |||||||
MX6 | MX5 | MX4 | MX3 | MX2 | MX1 | MX0 | ||
1 | 1 | 1 | 1 | 1 | x | x | eMMC boot | |
1 | 1 | 1 | 0 | 1 | x | x | SPI-NAND boot | |
1 | 1 | 0 | 1 | 1 | x | x | USB boot | |
1 | 1 | 0 | 0 | 1 | x | x | SDC boot | |
1 | 0 | 1 | 1 | 1 | x | x | SPI-NOR | |
1 | 0 | 0 | 0 | 1 | x | x | 8-bit NAND | |
Note:
If MX1 = 0, JTAG interface of CA55 of SP7350 will be enabled.
If MX2 = 0, SP7350 will enter test mode. Always set to 1 for normal operation.
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