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Under construction…

i-boot (internal boot code) is stored in the chip's internal mask ROM. Upon power-on reset, when the system initializes, the program counters of all CPUs (four ARM Cortex A55) are set to point to the entry point address of the i-boot program. Once the power-on reset deasserts, the CPUs start executing from the entry point address of the i-boot program. i-boot first initializes the CPU, sets up all interrupt vectors, initializes the stack, initializes the cache, configures serial ports, sets timers, and more. After initialization, it loads x-boot from external storage devices into SRAM and executes it.

A built-in ROM code.

Load x-boot image from a boot storage device into SRAM and run it.

Support 6 boot storage devices:

SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card

USB2.0 and USB3.0 flash drives

Support secure-boot.

Support encrypted x-boot.

CPU core 0 is the boot-core and is responsible for booting.

CPU core 1, 2 and 3 spin at i-boot until being waked up.

Support warm-boot (wake up from deep-sleep mode).

Features of i-boot

  1. Output log at UART0 at 115,200 bps.

  2. UART0 pins can be turned off by OTP bit.

  3. Read IV_MX[6..3] pins to decide boot-device.

  4. Support boot-devices: SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card, USB flash drive

  5. Support secure-boot.

    5.1. Verify digital signature of x-boot image.
    5.2. Decrypt x-boot image.

  1. Secure-boot is enabled by OTP bit.

  2. Support warm-boot.

  3. Support peripheral-reset signal (output from G_MX2).

Drivers

Features

8-bit NAND

  1. Support loading x-boot image from 8-bit NAND flash.

  2. First block of 8-bit NAND flash should contain Sunplus Boot Profile Header.

  3. Support reading 1K60 ECC sectors.

  4. x-boot image should be stored in 1K60 ECC sectors.

  5. Set MS control of pins of 8-bit NAND flash.

  6. Read cycle-time is 240 nS.

eMMC

  1. Load x-boot image from eMMC device.

  2. x-boot image should be stored at Boot Area Partition 1.

  3. Set MS control of pins of eMMC device.

  4. Bus clock is 25 MHz.

SPI-NAND

  1. Support loading x-boot image from SPI-NAND flash.

  2. First block of SPI-NAND flash should contain Sunplus Boot Profile Header.

  3. Support reading 1K60 ECC sectors.

  4. x-boot image should be stored in 1K60 ECC sectors.

  5. Support X1 and X2 position of SPI-NAND.

  6. Set MS control-bit of pins of SPI-NAND flash.

  7. Bus clock is 11.2 MHz.

SD card

  1. Support loading x-boot image from an SD card.

  2. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  3. File ISPBOOOT.BIN should be stored root directory of first partition of the SD card.

  4. First partition of the SD card should be FAT32 or FAT16 format.

  5. Bus clock is 5 MHz.

USB2.0 Host

  1. Support loading x-boot image from an USB flash drive in USB2.0 port.

  2. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  3. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive.

  4. First partition of the USB flash drive should be FAT32 or FAT16 format.

  5. Support high-speed read operation only

USB3.0 Host

  1. Support loading x-boot image from an USB flash drive in USB3.0 port.

  2. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  3. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive.

  4. First partition of the USB flash drive should be FAT32 or FAT16 format.

  5. Support high-speed read operation only

Boot core and others

CPU core 0 is the boot core.

CPU core 0 is responsible for all boot processes from i-boot to Linux.

CPU core 1, 2 and 3 spin (enter wfe mode) after initialize itself at i-boot.

image-20240122-034028.png

image-20240122-034050.png

Run Control of CPU Pen (at bootcompat session) :

image-20240122-034202.png

CPU_WAIT_INIT_VAL (0xffffffff)    // CPU waiting (spinning)

CPU_WAIT_A64_VAL (0xfffffffe)    // CPU goes to A64

x (address other than above)    // CPU goes to x

Bootstrap pins of SP7350

State of bootstrap pins of SP7350 will be read into bootstrap register (G0.31) at the moment that power-on reset is released. Refer to definition of boot-strap pins of SP7350 below:

Boot-strap pins of SP7350

Boot devices

MX6

MX5

MX4

MX3

MX2

MX1

MX0

1

1

1

1

1

x

x

eMMC boot

1

1

1

0

1

x

x

SPI-NAND boot

1

1

0

1

1

x

x

USB boot

1

1

0

0

1

x

x

SDC boot

1

0

1

1

1

x

x

SPI-NOR

1

0

0

0

1

x

x

8-bit NAND

Note:

  1. If MX1 = 0, JTAG interface of CA55 of SP7350 will be enabled.

  2. If MX2 = 0, SP7350 will enter test mode. Always set to 1 for normal operation.

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