This article provides a brief overview of the SP7350 software. Subsequent articles will delve into the detailed components of the software. The initial section begins with an introduction to software operations, followed by an explanation of CPU addressing space. The final will touch device address map.
Software operations
Software includes i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. The following figure illustrates the operation flow of i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. At power on, i-boot loads x-boot image from external storage device into SRAM, verify and executes it. x-boot first initializes SDRAM controller and trains SDRAM PHY. It then loads images of TF-A, OP-TEE and U-Boot from external storage device into DRAM and verify. Finally, it executes TF-A. TF-A invokes OP-TEE and then run U-Boot. U-Boot loads Linux image from external storage device into DRAM and executes it. After Linux boots up successfully, it loads firmware of CM4 (FreeRTOS) and then starts CM4.
Note that i-boot locates at chip internal mask ROM and is a part of hardware. x-boot, U-Boot only exist temporarily at boot time. Ubuntu server and ROS/ROS2 are optional. Afer system boots up successfully, software components stacked look like figure below.
CPU (Cortex A55) addressing space
CPU of SP7350 supports 16 GiB addressing space (with 34 address lines), including 8 GiB for DRAM and 4 GiB reserved for CPIO. The layout of the addressing space is depicted in 3 figures below: One is for 2 GiB DRAM, another is for 4 GiB DRAM, and the other is for 8 GiB DRAM. Let explain below sections.
Addressing space for 2 GB DRAM
Refer to figure below, in the first 4 GiB address space, the initial 2 GiB is allocated for the DRAM, while the remaining 0.25 GiB is reserved for chip internal devices and registers. The second and the forth 4 GiB address space are reserved (no use). The third GiB address space is for the device (or P-chip) which is connected with CPIO bus.
Addressing space for 4 GB DRAM
Refer to figure below, the first 0.75 GiB address space isallocated for the DRAM, followed by 0.25 GiB address space for chip internal devices and registers. The initial 0.25 GiB of the second 4 GiB address space is allocated for the DRAM, while the remaining 3.75 GiB is reserved (no use). The third 4 GiB address space is for the device (or P-chip) which is connected with CPIO bus. The last 4 GiB address space is reserved (no use).
Addressing space for 8 GB DRAM
Refer to figure below, the first 4 GiB address space is the same as the layout of 4 GiB DRAM. The second 4 GiB address space is allocated for the DRAM. The third 4 GiB address space is for the device (or P-chip) which is connected with CPIO bus. The initial 0.25 GiB of the last 4 GiB address space is allocated for the DRAM, while the remaining 3.75 GiB is reserved (no use).
Address map of devices and registers
The following figure provides a detailed view of the address map, starting from address 0xf0000000. It begins with 64 MiB of SPI-NOR flash (direct address space for NOR flash), followed by 64 MiB of SPI-NAND flash (direct address space for SPI-NAND flash), 8 MiB of device registers (such as OTP controller, SPI-NOR flash controller, SPI-NAND flash controller, eMMC controller, SD card controller, USB3 controller, etc.), 4 MiB of AO device registers (such as UART controller, RTC controller, I2C, SPI and etc.), 16 MiB of DDR SRAM controller registers, 1 MiB of Cortex-A55 registers, 1 MiB of Cortex-M4 registers, 256 KiB of CBDMA SRAM, 384 KiB of CM4 SRAM, 64 MiB 8-bit NAND flash controller and 96 KiB of ROM.
