x-boot

x-boot (external boot code) is a first-stage boot-loader placed in eMMC, NAND flash, or SD cards, loaded into system SRAM by i-boot. As it runs on SRAM, its size (including code, data, and stack) must not exceed the system SRAM's capacity. The primary task of x-boot is to initialize the DRAM controller and PHY, perform calibration on DRAM PHY and signals, and once calibrated, the DRAM is ready for use. x-boot then switches the CPU from 32-bit mode to 64-bit mode and loads TF-A and U-Boot from external storage into DRAM, executing TF-A.

x-boot (external boot code) is the first-stage boot loader. It is loaded into internal SRAM and run by internal ROM code of SP7350. Note that before X-Boot initializes and trains DRAM controller, DRAM is not available.

x-boot initializes and trains the SDRAM controller, preparing the DRAM for use. Subsequently, it loads the TF-A (Trusted Firmware-A) and OP-TEE (Open Portable Trusted Execution Environment) images from the fip (firmware image package) partition within ISPBOOOT.BIN, storing them in DRAM. Additionally, the U-Boot image is extracted from offset 0x30000 of ISPBOOOT.BIN and stored in DRAM. Upon successful checksum verification for all images, the system proceeds to execute TF-A, followed by OP-TEE, and finally U-Boot.

x-boot is loaded and run at SRAM before DRAM is available.

x-boot is responsible for doing DDR SDRAM training.

x-boot is responsible for loading U-Boot image.

x-boot is responsible for loading and running TF-A and OP-TEE OS.

Features

1. Output log at UART0 (at 115,200 bps).

2. Support accessing OTP using Sunplus OTPTool via UART0.

3. Support loading firmware of LPDDR4/DDR4/DDR3 from boot devices.

4. Support 1D and 2D training of LPDDR4, DDR4 and DDR3 SDRAM.

5. Support loading image of TF-A (BL31), OP-TEE (BL32) and U-Boot (BL33) from boot devices.

6. Support secure-boot:

   1. Verify digital signature of fip (TF-A and OP-TEE) and U-Boot images.

   2. Decrypt fip image.

7. Support warm-boot.

8. Switch CA55 to 64-bit mode and jump to run TF-A.

Drivers locations and features

Other files

All defconfig files are placed at configs/. Normally, the file name proceed with sp7350- and followed by defconfig, like sp7350_emmc_ev_defconfig, sp7350_sdcard_ev_defconfig, and etc.

Flow

SRAM Space Allocation

To facilitate program maintenance and data sharing, x-boot and i-boot utilize the same SRAM segment division and structure. Figure 4.2 illustrates the segmentation of SRAM into 9 segments, ranging from low to high addresses: xboot_buf, bootinfo, boothead, a64up, cdata, storage_buf, stack, bootcompat, and spacc_ram.

Below are explanations of each segment's purpose:

• xboot_buf: x-boot program segment, where the x-boot program is loaded and executed.

• bootinfo: bootinfo segment containing the g_bootinfo structure, which records boot-related information.

• boothead: boothead segment holding the g_boothead array, used to store GPT data for eMMC or header data for NAND flash.

• a64up: a64up segment where the a64up program resides, responsible for transitioning the CPU from 32-bit mode to 64-bit mode.

• cdata: C data segment containing global variables or static variables in C.

• storage_buf: Device driver data segment for boot devices such as eMMC and NAND flash. Different boot device drivers share the same space here during a single boot, as only one boot device driver is utilized per boot.

• stack: Stack segment where the stack for C is located.

• stack: Stack segment where the stack for C is located.

• spacc_ram: spacc data segment containing data used by SPAcc.

During system boot, i-boot reads boot-related information from the boot switch and the OTP (One-Time Programmable) memory within the C chip. This information is then stored in the g_bootinfo structure. Consequently, the data in the g_bootinfo structure determines the i-boot boot mode and the subsequent boot process. x-boot directly utilizes the data in the g_bootinfo structure to determine the boot mode and process.