C3V-W (LPDDR4) Dual EVB consists of two C3V-W chips. One is master which runs Linux software and the other is slave which provides extra 3.75 GiB DRAM, a NPU, and other peripherals (GPIO, clock, reset and etc.).
Table of Contents
1. Main Devices or Interfaces Description
The picture below is a photo of the C3V-W Dual EVB.
The following table explains briefly:
Items | Subsystem | Explanations |
1 | - | 12V DC power input. The diameter of the DC Jack plug is 5.5mm. The power supply current of the adapter must be greater than 1A. |
2 | - | Main-power switch. Turn down to ON, and turn up to OFF. |
3 | Slave | Pin-headers (3x1, 100mill) of GPIO of Slave C3V-W |
4 | Slave | CM4 console (UA6) of Slave C3V-W. Note GND is at the most bottom pin. It is default serial port of Cortex M4. The default baud rate is 115,200. No parity and 1 stop-bit. |
5 | Slave | Main console (UA0) of Slave C3V-W. Note GND is at the most bottom pin. This is default serial port of i-boot, x-boot, Trusted Firmware-A (TF-A), U-Boot and Linux kernel. The default baud rate is 115,200. No parity and 1 stop-bit. |
6 | Slave | 8 GiB LPDDR4 SDRAM of Slave C3V-W |
7 | - | Boot configuration switch |
8 | Master | Socket of micro SD card of Master C3V-W |
9 | Slave | Type C socket of USB 3.1 Gen1 of Slave C3V-W. It supports Low/Full/High/Super speeds, supports Host, Device and DRD. Current limit of VBUS is 1A. |
10 | Slave | Slave C3V-W chip (15mm x 15mm, 526-pin, TF-BGA) |
11 | Slave | 8 GiB eMMC of Slave C3V-W |
12 | Master | RJ-45 socket of Ethernet of Master C3V-W. It supports 10M/100M/1000M speeds. |
13 | Slave | Socket of micro SD card of Slave C3V-W |
14 | Master | 8 GiB eMMC of Master C3V-W |
15 | Master | Master C3V-W chip (15mm x 15mm, 526-pin, TF-BGA) |
16 | Master | Type C socket of USB 3.1 Gen1 of Master C3V-W. It supports Low/Full/High/Super speeds, supports Host, Device and DRD. Current limit of VBUS is 1A. |
17 | - | Reset key. Reset CM4 and main power-domains, but does not reset RTC. |
18 | Master | CM4 console (UA6) of Master C3V-W. Note GND is at the most left pin. It is default serial port of Cortex M4. The default baud rate is 115,200. No parity and 1 stop-bit. |
19 | Master | 8 GiB LPDDR4 SDRAM of Master C3V-W |
20 | Master | Main console (UA0) of Master C3V-W. Note GND is at the most right pin. This is default serial port of i-boot, x-boot, Trusted Firmware-A (TF-A), U-Boot and Linux kernel. The default baud rate is 115,200. No parity and 1 stop-bit. |
21 | Master | Pin-headers (3x1, 100mill) of GPIO of Master C3V-W. |
2. Descriptions for Pin-headers and Jumpers
Jumpers | Subsystem | Descriptions | Remarks |
J10 | Slave | Pin-headers (4 pins, 100 mil) for measuring current or voltage. |
|
J11 | Master | ||
J12 | Slave | ||
J13 | Master | ||
J14 | Slave | ||
J15 | Master |
| |
J26 | Master | Plug a jumper in to supply power for burning OTP of Master C3V-W chip. | No connect by default |
J31 | Slave | Plug a jumper in to supply power for burning OTP of Slave C3V-W chip. | No connect by default |
3. Boot Devices and Configuration
C3V-W Dual EVB supports boot from SD card and eMMC for both Master and Slave C3V-W. Refer to table below of selection of boot configuration switches for Master and Slave C3V-W.
Master | Slave | Boot Configuration Switch |
|---|---|---|
SD Card | SD Card |  |
SD Card | eMMC |  |
eMMC | SD Card |  |
eMMC | EMMC |  |
4. Map of Addressing Space of Master C3V-W.
Refer to map below for addressing space from view of Master C3V-W when 8 GiB LPDDR4 SDRAM is used:
The lowest 3.75 GiB space is mapped to the lower 3.75 GiB of the 8 GiB DRAM of Master C3V-W. The sequential 0.25 GiB space is for devices registers of Master C3V-W. Next 4 GiB space is mapped to upper 4 GiB of the 8 GiB DRAM of Master C3V-W. The 4 GiB space starting from address 0x2 0000 0000 is mapped to Slave C3V-W. The final 0.25 GiB space starting from address 0x3 0000 0000 is mapped to the remaining 0.25 GiB of the lower 4 GiB of the 4 GiB DRAM.
Address space starting from 0x2 0000 0000 is mapped to the lowest 4 GiB space of Slave C3V-W via CPIO interface. If CPU of Master C3V-W want to access DRAM of devices of Slave C3V-W, the base address of Slave C3V-W is from 0x2 0000 0000.
5. Setup CPIO Interface
CPIO interfaces are setup in x-boot for both Master and Slave C3V-W chip. For Master C3V-W, please run make xconfig at project top directory. Refer to picture below, when menu pops up, move cursor to “CPIO Mode” and select Master.
For Slave C3V-W, please run make xconfig at project top directory. Refer to picture below, when menu pops up, move cursor to “CPIO Mode” and select Slave.
6. Boot Flow of Software
