C3V-W Application Circuitry

Under Construction…

This document elucidates the application circuitry associated with the C3V-W. It serves as a supplementary resource to the specification of the C3V-W.

Contents

1. RTC

The C3V-W comes equipped with a built-in real-time clock (RTC) module, strategically placed within an independent power domain. This module is designed to remain powered continuously by an external power source such as a battery or super capacitor. This ensures uninterrupted functionality, even when other power domains are deactivated.

1.1 Power Requirements

Operating on a mere 1.8 volts, the RTC module is notably efficient. Its internal Low Dropout Regulator (LDO) generates a 0.8-volt power supply specifically for the RTC digital core. Refer to the schematic below for recommended power pin configurations, which necessitate the inclusion of bypass capacitors on the VDDPST18_GPIO_RTC and VDD_RTC pins.

1.2 32.768kHz Crystal

To work with precision, the RTC module requires connection to a 32.768 kHz crystal, alongside phase-shift circuitry, as illustrated in the schematic provided.

1.3 Wake-up Key Detection

The RTC module also boasts wake-up key detection functionality. When the CM4_WAKEUP_KEY pin is maintained at a HIGH state for 1 second, the CM4_PWR_EN pin is automatically set to HIGH by internal logic, activating power to the CM4 power domain. Refer to the timing charts below for a visual representation of this process.

Furthermore, if the CM4_WAKEUP_KEY pin remains HIGH for over 10 seconds, CM4_PWR_EN is forcibly set to LOW, effectively powering down the CM4 power domain. This functionality is depicted in the accompanying timing chart.

In addition to its hardware capabilities, the CM4 software incorporates default functionality as outlined below:

Refer to the schematic below for an example circuitry setup. In this configuration, the CM4_WAKEUP_KEY pin is linked to a physical key. Pressing the key pulls the CM4_WAKEUP_KEY signal to HIGH, while its default state remains LOW.

1.4 RTC_1V8 Power Supply

The schematic below illustrates a sample RTC_1V8 power supply circuitry. Drawing power from a source ranging from 3V to 5V, the system employs a super capacitor to store and deliver power during VCC downtimes. Resistor R16 (470Ω) regulates the charge current. Finally, a 1.8V low quiescent current LDO efficiently converts VCC_RTC to the required 1.8V power (RTC_1V8) for the RTC module's operation.

2. CM4 System

The CM4 system is equipped with an ARM Cortex M4 microcontroller and an array of interfaces, including 10 channels of I2C, 6 channels of SPI, 4 channels of PWM, 6 channels of UART, and 3 channels of audio I2S. The pins associated with these peripherals can be programmed to connect to either dual voltage IO (DVIO) pins or general-purpose IO (GPIO) pins.

Operating within its own independent power domain, the CM4 system is designed to remain functional even when the main power domain (comprising the CPU, NPU, video codec, MIPI-TX, MIPI-RX, USB3, etc. ) is powered off. The primary objectives of the CM4 system are as follows:

• Control the power on and off sequences of the main power domain.

• Communicate with Linux, running in the main power domain, via mailbox to facilitate entry into and resumption from deep-sleep mode (suspend to RAM).

• Manage peripherals and IO operations of the CM4 system, including external devices control and communication with other devices or microcontrollers.

• Monitor external events, such as signals from remote controllers and human voice commands.

2.1 Power Requirements

The CM4 system necessitates three power sources:

• 0.8V power for the digital core and system PLL (PLLS).

• 1.8V power for the ADC.

• Either 1.8V or 3.0V power for dual voltage IO (DVIO)

• 1.8V power for GPIO.

Refer to the schematic below for the recommended wiring of the 0.8V power supply for the digital core and system PLL. Notably, the AVDD08_PLLS power pin requires a ferrite bead on both the power and ground lines to ensure precise operational frequency and reduce clock jitter.

2.2 25MHz Crystal

The CM4 system needs a 25 MHz crystal accompanied by phase-shift circuitry, as depicted in the schematic below. This clock serves as the reference for various PLLs within the system, including PLLS (the system PLL), as well as PLLC, PLLL3, PLLD, PLLN, and PLLH, all located within the main power domain.

2.3 ADC

Featuring a four-channel, 12-bit analog-to-digital converter (ADC), the CM4 system requires a 1.8V power supply. It's recommended to incorporate a ferrite bead for power pin SAR12B_AVDD18 and separate grounding to filter out high-frequency noise, as depicted in the schematics.

2.4 DVIO (AO_MX0 ~ AO_MX29)

The DVIO pins are grouped into three categories, each with its own power supply and bias power pins. Consult the table provided for pin grouping details, ensuring appropriate connections with bypass capacitors.

The VDDPST18_DVIO_AO_x pins (where 'x' represents 1, 2, or 3) are designated for internal bias circuitry and necessitate connection to bypass capacitors. Simultaneously, the VDDPST3018_DVIO_AO_x pins (where 'x' represents 1, 2, or 3) require connection to a power supply of either 1.8V or 3.0V, supplemented by bypass capacitors.

2.5 GPIO, Bootstrap and RESET Pins

In addition to DVIO pins, the CM4 system includes a RESET pin, seven bootstrap pins, and nineteen GPIO pins. These pins are powered by two VDDPST18_GPIO_AO pins connected to a 1.8V power supply with bypass capacitors.

2.5.1 GPIO (AO_MX30 ~ AO_MX48)

These pins serve as 1.8V general-purpose IO (GPIO) pins and are prefixed with "AO_" indicating their association with the Always On (CM4) power domain. For ease of reference, consult the table below to determine the corresponding GPIO number for manipulation of IO registers.

2.5.2 Bootstrap Pins (IV_MX0 ~ IV_MX6)

The seven bootstrap pins encompass a variety of functions pertaining to boot device selection, CA555 JTAG interface activation, and chip test mode activation. Refer to the table below for the definition of each bootstrap pin regarding boot device selection:

(Note: "x" indicates "don't care" value)

When IV_MX2 is set to LOW, the C3V-W enters test mode, designated for internal use only. Likewise, when IV_MX1 is set to LOW, the CA55 JTAG interface pins are activated. IV_MX0 remains unused.

Following the de-assertion of the RESET pin, these pins can be repurposed as GPIOs. Refer to the table below for the corresponding GPIO numbers for IO registers manipulation.

2.5.3 Reset Circuitry

Pulling the RESET pin to LOW initiates a reset of the CM4 system, encompassing all components such as the Cortex M4, digital core, peripherals, DVIO, and GPIO pins. The schematic indicates the use of a voltage supervisor chip responsible for monitoring the 1.8V power supply.

The RESETB signal transitions to a deasserted state (HIGH) once the 1.8V power stabilizes and is ready for operation, a condition met after a typical duration of 107 milliseconds. Conversely, if the power supply fails to stabilize within this timeframe, the RESETB signal remains asserted (LOW), ensuring that the reset process is delayed until a stable power state is achieved.

2.5.4 Setup IO Voltage of Boot Device

The GPIO82 pin plays a crucial role in configuring the internal bias circuitry of DVIO pins utilized by boot devices. During the boot sequence execution, the i-boot (ROM code) reads the state of this pin to establish the bias circuitry of the DVIO pins associated with the boot device.

For systems utilizing a 1.8V IO boot device, it is necessary to connect the GPIO82 pin to GND through a 4.7 kΩ pull-down resistor. This configuration ensures proper setup of the bias circuitry for compatibility with the 1.8V IO boot device. Conversely, if employing a 3.3V IO boot device, it is essential to leave the GPIO82 pin open to maintain compatibility with the higher voltage requirement of the boot device.

3. Powers for Main System

The main system encompasses all components except for the RTC module and CM4 system. This includes the ARM Cortex A55, DDR SDRAM controller, NPU (VIP9000), video codec, GMAC, USB3, USB3, MIPI-RX, MIPI-TX, eMMC, SD card, SDIO and NAND flashes controller and etc.

3.1 Power Requirements for PLL, Thermal Sensor, and OTP Burning

Refer to the schematic below for the recommended power configuration. Provide a 0.8V power supply for PLLs (AVDD08_PLLC and AVDD08_PLLD) and a 1.8V power supply for the thermal sensor (TML_AVDD18) and OTP burning (OTP_1V8). Bypass capacitors are essential to filter out high-frequency noise from the power supply lines.

AVDD08_PLLC powers PLLC (the CPU PLL), PLLL3 (the CPU L3 cache PLL), PLLH (the peripheral PLL), and PLLN (the NPU PLL). Similarly, AVDD08_PLLD powers PLLD (the DRAM PLL). Both require ferrite beads on the power and ground lines for stability and reduced clock jitter.

3.2 Power Requirements for System, Video-Codec, CA55 and NPU

The recommended power wiring for VDD (system digital core), VDD_VV (video codec), VDD_CA55 (CPU CA55), and VDD_NPU (NPU) is detailed in the schematic below. Bypass capacitors are crucial to provide a low-impedance path to ground and reduce voltage ripple when high current is drawn.

Refer to the table below for the target impedance for each power domain, ensuring optimal performance:

Each power domain operates independently and can be powered on or off individually. Note that VDD powers the system digital core, including the AXI bus and top-level components. It should be powered on first, followed by CA55, NPU, and the video codec for proper functionality.

Additionally, the VDD_NPU_MEASURE signal, a subset of the VDD_NPU pin, serves the specific purpose of providing feedback on the VDD_NPU voltage to the DC2DC regulator for precise control.

4. GPIO and DVIO of Main System

The main system features 20 General Purpose IO (GPIO) pins and 18 Dual Voltage IO (DVIO) pins. GPIO operates at 1.8V, while DVIO offers the flexibility of operating at either 1.8V or 3.0V, accommodating various voltage requirements.

In addition to serving as IO pins, interface pins of devices within the CM4 system or main system can be configured to connect to GPIO or DVIO pins. This adaptability facilitates seamless integration, enhancing overall flexibility and functionality within the system architecture.

4.1 GPIO (G_MX0 ~ GMX19)

GPIO pins are powered by two VDDPST18_GPIO_0 and VDDPST18_GPIO_1 power pins, which should be connected to a 1.8V power supply with bypass capacitors for stable operation.

For ease of reference, consult the table below to determine the corresponding GPIO number for manipulation of IO registers:

Moreover, the G_MX2 (GPIO2) pin fulfills a specialized role in resetting peripherals by generating a 10-millisecond LOW pulse during system reboots. A dedicated driver is incorporated into GPIO2 to manage the PER_RESET (low-active) signal effectively. Refer to the following schematics for further details.

4.2 DVIO (G_MX20 ~ GMX37)

The DVIO pins are divided into two groups, each with its own power supply and bias power pins. Refer to the table provided for pin grouping details:

Ensure appropriate connections with bypass capacitors for stable operation. The VDDPST18_DVIO_x pins (where 'x' represents 1 or 2) are designated for internal bias circuitry, while the VDDPST3018_DVIO_x pins (where 'x' represents 1 or 2) require connection to a power supply of either 1.8V or 3.0V, supplemented by bypass capacitors.

Refer to the schematics for visual guidance.

5. DDR SDRAM

The DDR SDRAM controller of C3V-W support five types of DDR SDRAM: LPDDR4, DDR4, LPDDR3, DDR3, and DDR3L.

Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.

5.1 Data Bus and Data Strobe Signals Wiring

Refer to the table below for the wiring of data bus and data strobe signals for different types of DDR SDRAM.

5.2 Address Bus and Control Signals Wiring

The table below illustrates the wiring of address bus and control signals for various types of DDR SDRAM.

5.3 LPDDR4 Circuitry

5.3.1 DDR PHY of C3V-W

Please refer to the schematics for the connection details of power, command address bus, data bus, and clocks of the DDR PHY.

• The DRAM_VDD power pins are designated for the digital core of the DDR PHY. It is essential to connect these pins to a 0.8V power source and include bypass capacitors for stable operation.

• The DRAM_VDDQ power pins cater to the IO buffers of the DDR PHY. These pins must be connected to a 1.1V power source and equipped with bypass capacitors to ensure optimal performance.

• The BP_VAA power pin serves the PLL of the DDR PHY. It is crucial to connect this pin to a 1.8V power source and include bypass capacitors to maintain stable PLL operation.

Refer to the table below for the operational range of each power source:

It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:

Adhering to these target impedance values ensures optimal performance and reliability of the DDR PHY within the PCB design.

5.3.2 CA and Data Signals of LPDDR4 SDRAM

Please refer to the schematics for the connection of power, control, address bus, and data bus of LPDDR4 SDRAM.

5.3.3 Power and Ground of LPDDR4 SDRAM

The VDD1 (1.8V), VDD2 (1.1V), and VDDQ (1.2V) power lines of LPDDR4 SDRAM require numerous bypass capacitors to enhance signal integrity by mitigating signal reflections and ringing on the power supply lines. Please refer to the schematics provided below for further details.

5.4 DDR4 Circuitry

5.4.1 DDR PHY of C3V-W

Please refer to the schematics for the connection details of power, address bus, data bus, and control signals of the DDR PHY.

• The DRAM_VDD power pins are designated for the digital core of the DDR PHY. It is essential to connect these pins to a 0.8V power source and include bypass capacitors for stable operation.

• The DRAM_VDDQ power pins cater to the IO buffers of the DDR PHY. These pins must be connected to a 1.2V power source and equipped with bypass capacitors to ensure optimal performance.

• The BP_VAA power pin serves the PLL of the DDR PHY. It is crucial to connect this pin to a 1.8V power source and include bypass capacitors to maintain stable PLL operation.

Refer to the table below for the operational range of each power source:

It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:

Adhering to these target impedance values ensures optimal performance and reliability of the DDR PHY within the PCB design.

5.4.2 Address and Data Signals of DDR4 SDRAM

Please refer to the schematics for the connection of power, address bus, data bus, and control signals of the DDR PHY. Two DDR4 SDRAM chips are utilized to form a 32-bit width data bus. Besides, the T-topology methodology is employed to route the address signals from the PHY to the two SDRAM chips.

5.4.3 Clock Termination

Please refer to the schematics provided below. The clock signal differential pair of DDR4 SDRAM (DRAM_CLK0_T and DRAM_CLK0_C) requires AC termination with a differential impedance of 100Ω. Additionally, the T-topology methodology is employed to route the clock signals from the PHY to the two SDRAM chips.

5.4.4 SDP or DDP Selection

Please refer to the schematics provided below. Resistors Re9, Rm9, and Rm9b are utilized for configuring either the Single Die Package (SDP) or Dual Die Package (DDP) DDR4 SDRAM.

The table below offers a detailed configuration guide for SDP or DDP DDR4 SDRAM:

5.4.5 Bypass Capacitors for VDDQ Power of DDR4 SDRAM

The VDDQ power of DDR4 SDRAM requires numerous bypass capacitors to enhance signal integrity by mitigating signal reflections and ringing on power supply lines. Please refer to the schematics provided below for further details.

VPP1 and VPP2 power require bypass capacitors to effectively filter out high-frequency noise present in the power supply lines.

5.5 DDR3/DDR3L Circuitry

5.5.1 DDR PHY of C3V-W

Please refer to the schematics for the connection details of power, address bus, data bus, control signals and clock of the DDR PHY.

• The DRAM_VDD power pins are designated for the digital core of the DDR PHY. It is essential to connect these pins to a 0.8V power source and include bypass capacitors for stable operation.

• The DRAM_VDDQ power pins cater to the IO buffers of the DDR PHY. These pins must be connected to a 1.35V power source for DDR3L (or a 1.5V power source for DDR3) and equipped with bypass capacitors to ensure optimal performance.

• The BP_VAA power pin serves the PLL of the DDR PHY. It is crucial to connect this pin to a 1.8V power source and include bypass capacitors to maintain stable PLL operation.

Refer to the table below for the operational range of each power source:

It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:

Adhering to these target impedance values ensures optimal performance and reliability of the DDR PHY within the PCB design.

5.5.2 Address and Data Signals of DDR3 SDRAM

Please refer to the schematics for the connection of power, address bus, data bus, and control signals of DDR3 SDRAM. Two DDR3 SDRAM chips are utilized to form a 32-bit width data bus. Besides, the T-topology methodology is employed to route the address signals from the PHY to the two SDRAM chips.

5.5.3 Clock Termination

Refer to schematics below, the differential-pair clock signal of DDR3 SDRAM (DRAM_CLK0_T and DRAM_CLK0_C) requires AC termination with a differential impedance of 100Ω. Furthermore, the T-topology methodology is utilized to route the clock signal from the PHY to the two SDRAM chips.

5.5.4 Bypass capacitors for VDD and VDDQ power of DDR3 SDRAM

The VDD and VDDQ power lines of DDR3 SDRAM require numerous bypass capacitors to enhance signal integrity by mitigating signal reflections and ringing on the power supply lines. Please refer to the schematics provided below for further details.

6. eMMC

The C3V-W supports booting from an eMMC device. To boot from the eMMC device, set the bootstrap pins IV_MX[6:2] to [1 1 1 1 1]. The default sector size of the eMMC is 512 bytes, and the maximum supported capacity is 128 GB. The device achieves a maximum speed of HS200 (SDR-200MHz) or DDR-133MHz when using a 1.8V IOVDD.

6.1 eMMC Interface of C3V-W

The eMMC device's interface pins connect to GPIO20, GPIO28 ~ GPIO37, corresponding to D5, D3, D4, D0, D1, CLK, D2, D7, D6, CMD, and DS signals. GPIO37 is necessary only for HS400 mode.

The VDD_DVIO_2 power group, comprising GPIO20 and GPIO28 to GPIO37 pins, supports both 1.8V and 3.3V operations.

6.2 eMMC Chip

For eMMC chip wiring, refer to the provided schematics. Connect the VDD power pins of the eMMC chip to the power pins (VDD_DVIO_2) of GPIO20, GPIO28 to GPIO37. The VDDF power pins should be connected to a 3.3V power source. Make sure to connect all power pins to bypass capacitors. This ensures stable operation and improves signal integrity by minimizing signal reflections and ringing on the power supply lines.

The RSTN (device reset) pin connects to the peripheral reset signal, PER_RESETB, to trigger a reset during system reboots, ensuring the eMMC device boots successfully.

If the eMMC device isn't used, the interface pins can function as DVIO pins.

6.3 Pull-up Resistors

It's advisable to add 51 kΩ pull-up resistors for SDIO data and command signals by default.

7. SD Card

The C3V-W also supports SD cards for booting. The default sector size is 512 bytes, and the maximum capacity is 128 GB. To boot from an SD card, set the bootstrap pins IV_MX[6:2] to [1 1 0 0 1]. The maximum operation speed is SDR-200MHz (100MB/s).

7.1 SD Card Port of C3V-W

Refer to the provided schematics for the detailed SD card interface and power connections. The SD card's interface pins connect to GPIO38 ~ GPIO43 for D1, D0, CLK, CMD, D3, and D2 signals. Supply the AVDD30_SD_SDIO power pin with 3.0V, using bypass capacitors for stability. VDDPST18_SD and VDDPST18IO_SD pins are for internal bias circuitry and should also connect to bypass capacitors.

If the SD card interface isn't used, the interface pins can function as DVIO pins.

7.2 Micro SD Card Socket

Refer to the schematics for micro SD card connections. SD card interface signals should follow the micro SD card socket's pin-out. The SD (VCC) pin requires a 3.3V power supply with bypass capacitors for stability. The SD_IN pin detects card insertion, connecting to a GPIO pin.

7.3 Pull-up Resistors

For SD card data and command signals, it's recommended to add 30kΩ pull-up resistors by default.

7.4 Power Control

The SD card's power is controlled by the peripheral reset signal, PER_RESETB. When PER_RESETB is asserted (LOW), the SD card power turns off and turns on when de-asserted. This circuitry helps recover the SD card from an unknown state, ensuring successful booting.

If the SD card isn't a boot device, this power control circuitry isn't necessary.

8. SDIO

The C3V-W supports an SDIO interface with a maximum operation speed of SDR-200MHz (100MB/s). Connect it to any SDIO interface device, such as an SDIO interface WiFi chip.

8.1 SDIO Port of C3V-W

Refer to the provided schematics for detailed SDIO interface and power connections. The SDIO interface pins are multiplexed with GPIO44 ~ GPIO49 for D1, D0, CLK, CMD, D3, and D2 signals. The AVDD30_SD_SDIO power pin shares power with the SD card interface and requires a 3.0V supply with bypass capacitors for stability. VDDPST18_SDIO and VDDPST18IO_SDIO pins are for internal bias circuitry and should also connect to bypass capacitors.

If the SD card interface isn't used, the interface pins can function as DVIO pins.

8.2 Pull-up Resistors

For SDIO data and command signals, it's recommended to add 30kΩ pull-up resistors by default.

9. SPI-NOR Flash

The C3V-W supports SPI-NOR flash for booting. For booting from an SPI-NOR flash, configure the bootstrap pins IV_MX[6:2] to [1 0 1 1 1]. The C3V-W accommodates a maximum capacity of 64 MB for SPI-NOR flash and operates at up to 102 MHz when using a 1.8V SPI-NOR flash chip. It is recommended to use 1.8V flash chip for high speed operation.

9.1 SPI-NOR Interface of C3V-W

The interface pins for the SPI-NOR flash connect to GPIO21 ~ GPIO26, corresponding to D2, CLK, D1, D3, CSB, and D0 signals.

The VDD_DVIO_1 power group, comprising GPIO21 to GPIO27 pins, supports both 1.8V and 3.3V operations.

9.2 SPI-NOR Flash Chip

For wiring the SPI-NOR flash, consult the provided schematics. Connect the VDD power pins of the SPI-NOR flash to the FLASH_SW power source derived from VDD_DVIO_1 power of GPIO21 to GPIO26. Ensure the power pin connect to bypass capacitors to maintain stable operation and enhance signal integrity by reducing signal reflections and ringing on the power supply lines. For D2, D3, and CSB signals, it's recommended to include 10kΩ pull-up resistors by default.

If the SPI-NOR flash interface isn't utilized, these pins can serve as DVIO pins.

9.3 Power Control

Power to the SPI-NOR flash is managed by the peripheral reset signal, PER_RESETB. When PER_RESETB is active (LOW), the SPI-NOR flash power is disabled, and it's enabled when the signal is inactive. This power control circuitry aids in recovering the SPI-NOR flash from an indeterminate state, ensuring a successful boot.

If the SPI-NOR flash isn't used as a boot device, this power control circuitry is not required.

10. SPI-NAND Flash

The C3V-W supports SPI-NAND flash for booting. To boot from an SPI-NAND flash, set the bootstrap pins IV_MX[6:2] to [1 1 1 0 1]. The C3V-W supports either 2k-sector with 1 or 2 planes or 4k-sector with 1 plane. When using a 1.8V flash chip, the maximum clock frequency is 153 MHz. It's advisable to use a 1.8V flash chip for optimal high-speed operation.

10.1 SPI-NAND Interface of C3V-W

The SPI-NAND flash interface pins connect to GPIO30 ~ GPIO35, corresponding to D0, D2, CLK, D1, D3, and CSB signals.

The VDD_DVIO_2 power group, comprising GPIO20 and GPIO28 to GPIO37 pins, supports both 1.8V and 3.3V operations.

The C3V-W also supports a second pin-out for SPI-NAND flash, using the same interface pins as SPI-NOR flash. These connect to GPIO21 ~ GPIO26 for D2, CLK, D1, D3, CSB, and D0 signals. The existing circuitry for SPI-NOR flash can be used interchangeably with SPI-NAND flash.

The VDD_DVIO_1 power group, comprising GPIO21 to GPIO27 pins, supports both 1.8V and 3.3V operations.

10.2 SPI-NAND Flash Chip

For wiring the SPI-NAND flash, refer to the provided schematics. Connect the VDD power pins of the SPI-NAND flash to the SPINAND_SW power source derived from VDD_DVIO_2 power of GPIO30 to GPIO35. Ensure power pins connect to bypass capacitors for stable operation and improved signal integrity. For D2, D3, and CSB signals, include 10kΩ pull-up resistors by default.

If the SPI-NAND flash interface is unused, these pins can function as DVIO pins.

10.3 Power Control

Power to the SPI-NAND flash is controlled by the peripheral reset signal, PER_RESETB. When PER_RESETB is active (LOW), the SPI-NAND flash power is disabled and enabled when the signal is inactive. This power control mechanism assists in recovering the SPI-NAND flash from an undefined state, ensuring successful booting.

If the SPI-NAND flash is not used for booting, this power control circuitry is unnecessary.

11. 8-bit NAND Flash

The C3V-W supports booting from 8-bit NAND flash. To boot from an 8-bit NAND flash, set the bootstrap pins IV_MX[6:2] to [1 0 0 0 1]. The C3V-W is compatible with 2k-sector, 4k-sector, or 8k-sector NAND flash. For optimal high-speed performance, it's recommended to use a 1.8V VCCQ power supply.

11.1 8-bit NAND Interface of C3V-W

The 8-bit NAND flash interface connects to GPIO20, GPIO21, GPIO23 to GPIO36, corresponding to RDY0, WP_B, RE_B, CLE, ALE, WE_B, D0 to D7, DQS, and D4 to D7 signals.

Note that the 8-bit NAND uses both the VDD_DVIO_1 power group (GPIO21 to GPIO27) and the VDD_DVIO_2 power group (GPIO20, GPIO28 to GPIO37). Both power groups should receive the same voltage, either 1.8V or 3.3V.

11.2 SPI-NAND Flash Chip

For wiring the 8-bit NAND flash, refer to the provided schematics. Connect the VCC_x (where x ranges from 1 to 8) power pins to 3.3V. Connect VCCQ_x (where x ranges from 1 to 8) to the FLASH_SW power source derived from VDD_DVIO_1 (GPIO21 to GPIO27). Ensure that both VCC_x and VCCQ_x power pins are connected to bypass capacitors for stable operation and improved signal integrity. The RE_B signal should have a default 10kΩ pull-up resistor.

If the 8-bit NAND flash interface is unused, these pins can serve as DVIO pins.

11.3 Power Control

The power for the 8-bit NAND flash shares circuitry with the SPI-NOR flash power control. It's governed by the peripheral reset signal, PER_RESETB. When PER_RESETB is active (LOW), the power to the 8-bit NAND flash is disabled, and it's enabled when the signal is inactive. This power control mechanism helps recover the 8-bit NAND flash from an indeterminate state, ensuring successful booting.

12. UART Console

By default, UART0 serves as the system's main console (CA55), while UART6 serves as the console for FreeRTOS (CM4).

12.1 Main Console

i-boot (ROM code), x-boot, BL31 (TF-A), OP-TEE, U-Boot, and Linux utilize UART0 as their console. Note that i-boot, being ROM code, is not modifiable by users. Users can only alter x-boot, BL31 (TF-A), OP-TEE, U-Boot, or Linux to use a different UART as the system's main console.

12.1.1 UA0 Pins of C3V-W

UART0 is set to use GPIO50 (TXD) and GPIO51 (RXD) by default.

GPIO50 and GPIO51 are dual-voltage IO pins belonging to the VDD_DVIO_AO_1 power group.

12.1.2 Voltage Translator and UA0 Port

The voltage translator for UART0 consists of Si2302 (N-channel MOSFET) and resistors, which convert the signal levels of UART0 from VDD_DVIO_AO_1 (either 1.8V or 3.0V) to 3.3V and vice versa.

If VDD_DVIO_AO_1 uses 3.3V power, the voltage translator is unnecessary.

12.2 CM4 Console

FreeRTOS uses UART6 as its default console. Users have the flexibility to modify the FreeRTOS software to utilize a different UART as the console.

12.2.1 UA6 Pins of C3V-W

UART6 is configured to use GPIO80 (TXD) and GPIO81 (RXD) by default.

GPIO80 and GPIO81 are 1.8V power GPIO pins belonging to the AO_1V8 power group.

12.2.2 Voltage Translator and UA6 Port

The voltage translator for UART6 consists of Si2302 (N-channel MOSFET) and resistors, converting the signal levels of UART6 from AO_1V8 (1.8V) to SYS_3V3 (3.3V) and vice versa.

13. USB2.0

13.1 USB2.0 Port of C3V-W

13.2 Type A Receptacle

13.3 VBUS of Type A Receptacle

13.4 Micro-AB Receptacle

13.5 VBUS of Micro-AB Receptacle

13.6 OTG

14. USB3.0

14.1 USB3.0 Port of C3V-W

14.2 Type C Receptacle

14.3 VBUS of Type C Receptacle

14.4 CC Detection Circuitry

15. MIPI-RX4

15.1 MIPI-RX4 Port of C3V-W

15.2 15-Pin Camera Connector (2d2c) of Raspberry Pi

16. MIPI-RX5

16.1 MIPI-RX5 Port of C3V-W

16.2 22-Pin Camera Connector (4d1c) of Raspberry Pi

17. CPIO and MIPI-RX2/RX3

17.1 CPIO Port of C3V-W

17.1.1 Swap Mode Connection

17.1.2 Crossover Mode Connection

17.2 MIPI-RX2 and MIPI-RX3

18. MIPI-TX

18.1 MIPI-TX Port of C3V-W

18.2 15-Pin Display Connector (2d2c) of Raspberry Pi

19. CA55 JTAG Interface

The C3V-W board supports the JTAG ICE interface for Cortex A55 (CA55). This interface enables developers to perform real-time debugging by connecting to the CA55 processor's JTAG (Joint Test Action Group) interface.

19.1 CA55 JTAG Pins

The interface pins are mapped to GPIO13 to GPIO17, corresponding to the TRST_N, TMS, TCK, TDI, and TDO signals of JTAG.

To activate the JTAG interface, users should configure G1.1[8] to 1 or set bootstrap pin IV_MX[1] to 0. Please note that the JTAG interface pins share functionality with RGMII pins and cannot be used simultaneously.

19.2 CA55 JTAG Pin-header

Referring to the schematics below, the standard JTAG connector is a 2x10-pin 100mil-pitch pin-header. Pin 1 serves as the reference voltage for JTAG signals, while Pin 2 provides optional VCC power. The JTAG_nSRST signal (low-active), derived from the RESETB signal, functions as the system reset. It's important to note that the CA55 JTAG signals operate at 1.8V.

20. CM4 JTAG/SWD Interface

The C3V-W also supports the JTAG and SWD ICE interfaces for Cortex M4 (CM4). Both interfaces allow developers to debug their target systems in real-time. JTAG is the traditional interface, while SWD (Serial Wire Debug) is a two-wire protocol designed specifically for ARM processors, offering an alternative when pin resources are limited or PCB layout is constrained.

20.1 CM4 JTAG/SWD Pins

For JTAG, the interface pins are GPIO88 to GPIO93, corresponding to TRST_N, TMS, TCK, TDI, and TDO signals. For SWD, the pins are GPIO89, GPIO90, and GPIO93, corresponding to SWDIO, SWCLK, and SWDO signals.

To activate the JTAG interface, users should configure G1.5[0] to 1.

20.2 CM4 JTAG and SWD Pin-header

Referring to the schematics below, the standard JTAG/SWD connector is a 2x10-pin 100mil-pitch pin-header. Pin 1 provides the reference voltage for JTAG signals, and Pin 2 offers optional VCC power. Similar to CA55, the CM4_JTAG_nSRST signal (low-active) for system reset is derived from the RESETB signal. Note that the CM4 JTAG signals operate at 1.8V.

21. UA2AXI Interface

The UA2AXI interface is a proprietary UART interface by Sunplus that connects to the internal AXI bus of the C3V-W. The UA2AXI interface shares its interface with UADBG (UART5), which is a standard UART and can be probed by Linux.

21.1 UA2AXI Pins of C3V-W

The interface pins for UA2AXI are GPIO13 (TXD) and GPIO14 (RXD). Both GPIO13 and GPIO14 are 1.8V power GPIO pins belonging to the SYS_1V8 power group.

21.2 Voltage Translator and UA2AXI Port

The voltage translator for UA2AXI comprises the Si2302 (N-channel MOSFET) and resistors, which convert the signal levels of UA2AXI from SYS_1V8 (1.8V) to SYS_3V3 (3.3V) and vice versa.