Preface
This manual describes how to use the C3V-W Evaluation Board (EVB). This evaluation board is used for IP verification and software functions testing of the C3V-W chip. IP verification includes all IP tests in the chip, chip boot modes test, all GPIO, DVIO pins (UART, I2C, SPI, …) testing and multiplexed functional pins test, USB2.0, USB3.0, CPIO, MIPI/CSI-RX2, MIPI/CSI-RX3, MIPI/CSI-RX4, MIPI/CSI-RX5, MIPI/DSI-TX, and MIPI/CSI-TX and other interface tests. Software functions include i-boot, x-boot, U-Boot, TF-A, OP-TEE, FreeRTOS, Linux, Ubuntu server with MATE desktop and other related application tests.
Table of Contents
1. Main Devices or Interfaces Description
The picture below is a photo of the C3V-W EVB.
The following table explains briefly:
Items | Explanations |
1 | 12V DC power input. The diameter of the DC Jack plug is 5.5mm. The power supply current of the adapter must be greater than 1A. |
2 | Main-power switch. Turn left to ON, and turn right to OFF. Note that you still need to press Wake-up key (for 1 second) to wake up the system after turning on main-power switch. |
3 | Wake-up key. The functions are as follows:
|
4 | Socket (DIP-8) of SPI-NOR flash chip. Before inserting the SPI-NOR flash chip, be sure to confirm the chip notch direction (or pin 1 position) and the chip power supply voltage (1.8V or 3.3V). There is a SOIC-8 soldering pad under the DIP-8 socket. The DIP-8 socket can be removed and used a SOIC-8 SPI-NOR chip instead Note that to test frequencies of SPI-NOR flash above 60MHz, please use SOIC-8 packaged chips. |
5 | Socket of micro SD card. |
6 | RJ-45 socket of Ethernet. It supports 10M/100M/1000M speeds. |
7 | Giga PHY chip of Ethernet (Realtek RTL8211FD). |
8 | Pin-header (3-pin, 100-mil, 3.3V) of UADBG/UA2AXI (serial port). The pin definitions from left to right are TX, RX, and GND. It can be used as general UART (UADBG) or UART-to-AXI bridge UART (UA2AXI). The default baud rate is 115,200. No parity and 1 stop-bit. Software uses it as an OP-TEE serial port interface for debugging client applications of OP-TEE. Please note that EVB does not use the UADBG/UA2AXI serial port by default. To use the UADBG/UA2AXI serial port, please solder 0Ω resistors at the R411 and R412 positions, and remove the 0Ω resistors at the R348 and R349 positions. In addition, be care of pin-mux settings in software, UADBG/UA2AXI cannot be used with the CA55 JTAG or GMAC interface at the same time. Make sure both CA55 JTAG and GMAC interfaces are off. |
9 | Socket (DIP-24, 600 mil) of daughter board of 8-bit NAND flash. Please refer to Appendix 3 for pin definitions. Before inserting the daughter board of 8-bit NAND flash, be sure to confirm the notch direction of the daughter board (or pin 1 position) and the chip power supply voltage (1.8V or 3.3V). |
10 | Socket (DIP-8) of daughter board of SPI-NAND flash. Before inserting the SPI-NAND flash chip, be sure to confirm the chip notch direction (or pin 1 position) and the chip power supply voltage (1.8V or 3.3V). There is a WSON-8 soldering pad of SPI-NAND flash under the socket, and the DIP-8 socket can be removed and replaced with a WSON-8 packaged SPI-NAND chip. Note that to test frequencies of SPI-NAND flash above 60MHz, please use WSON-8 packaged chips. |
11 | Socket (DIP-24, 600 mil) of daughter board of eMMC. Please refer to Appendix 2 for pin definitions. Before inserting the eMMC daughter board, be sure to confirm the direction of the daughter board notch (or pin 1 position). There is an FGBA-153 soldering pad of eMMC chip under the socket. The DIP-24 socket can be removed and replace with a FBGA-153 packaged eMMC chip. Note that to test speed above DDR52 or HS100, please use FBGA packaged chips. |
12 | Pin-header (10x2 pins, 100 mil) of JTAG interface of Cortex-A55. Please refer to Appendix 1 for pin definitions. Before inserting the JTAG cable, be sure to confirm the position of pin 1. |
13 | Type A socket of USB 2.0. It supports Full/High speeds, supports Host, Device and OTG 1.0. Current limit of VBUS is 1A. |
14 | Micro AB socket of USB 2.0. It supports Full/High speeds, supports Host, Device and OTG 1.0. Current limit of VBUS is 1A. Please note that USB 2.0 Type A and Micro AB sockets share the same USB 2.0 port, and only one of them can be used at a time. |
15 | Type C socket of USB 3.1 Gen1. It supports Low/Full/High/Super speeds, supports Host, Device and DRD. Current limit of VBUS is 1A. |
16 | WiFi/Bluetooth (AMPAK AP6256) module. Main chip of the module is Broadcom BCM43456 chip. |
17 | Pin-header (3-pin, 100-mil, 3.3V) of UART0 (serial port of main console). The pin definitions from left to right are GND, RX, and TX. It is default serial port of i-boot, x-boot, Trusted Firmware-A (TF-A), U-Boot and Linux kernel. The default baud rate is 115,200. No parity and 1 stop-bit. |
18 | Samtec differential socket (QSH-020-01-F-D-DP) of CPIO. CPIO is a high-speed (4.8 GB/s) interface for connecting to a peripheral chip. Chip-to-chip (external mode, on board) transfers support a maximum speed of 4.8 GB/s, and die-to-die (internal mode, in a package) transfers support a maximum speed of 9.6 GB/s. Refer to Section 11 for details. |
19 | FFC connector (15 pins, 1.0mm) of MIPI/CSI-RX4 interface. It is compatible with the Raspberry Pi camera FFC connector. Please refer to Appendix 5 for pin definitions. |
20 | FFC connector (24-pin, 0.5mm, top-contact) of MIPI/CSI-RX5. Please refer to Appendix 6 for pin definitions. |
21 | FFC connector (15-pin, 1.0mm) of MIPI/DSI-TX interface. It is compatible with the Raspberry Pi display FFC connector. Please refer to Appendix 7 for pin definitions. |
22 | FFC connector (30-pin, 0.5mm, top-contact) of MIPI/DSI-TX interface. The interface also supports MIPI/CSI-TX functionality. Please refer to Appendix 7 for pin definitions. Please note that both MIPI/DSI-TX connectors (J21 and J22) share the same MIPI/DSI-TX interface and cannot be used at the same time. |
23 | C3V-W chip (15mm x 15mm, 526-pin, TF-BGA). |
24 | Pin-header (2x10, 100mill) of Audio. Please refer to Appendix 4 for pin definitions. |
25 | Pin-header (3-pin, 100-mil, 3.3V) of UART6 (serial port). The pin definitions from top to bottom are GND, RX, and TX. It is default serial port of Cortex M4. The default baud rate is 115,200. No parity and 1 stop-bit. |
26 | Reset key. Reset CM4 and main power-domains, but does not reset RTC. |
27 | Boot configuration switch (SW2) of C3V-W chip. Please refer to Section 3 "Boot Device and Configuration" for boot configuration switch setting. |
28 | Boot configuration switch (SW3) of C3V-W chip. Please refer to Section 3 "Boot Device and Configuration" for boot configuration switch setting. |
29 | Pin-header (2x10 pins, 100 mil) of JTAG interface of Cortex M4. Before inserting the JTAG cable, please be sure to confirm the position of pin 1. Please refer to Appendix 9 for pin definitions. |
30 | Micron LPDDR4 SDRAM (3200Mbps). The C3V-W chip supports three types of DDR SDRAM, including LPDDR4, DDR4 and DDR3, with a maximum size of 8 GiB. |
31 | Pin-headers of 1.8V ←→ 3.3V/3.0V bi-directional voltage-translators. |
2. Descriptions for Pin-headers and Jumpers
Jumpers | Descriptions | Remarks |
J1, J2, J4, J6, J7, J9, J10, J12, J13, J14, J15 | Pin-headers (4 pins, 100 mil) for measuring current or voltage. |
|
J3 | Pin-header (2 pins, 100 mil) for feeding external +12V DC power directly. | No use by default |
J5 | When plug a jumper in J5, the CM4 (AO) domain power supply is controlled by the CM4_PWR_EN signal. | Plug a jumper in |
J8 | When plug a jumper in J8, the VDD_VV (video codec) power is controlled by the VV_PWR_EN signal. | Plug a jumper in when need. |
J11 | When plug a jumper in J11, the VDD_NPU (NPU) power is controlled by the CM4_PWR_EN signal. | Plug a jumper in when need. |
J16, J17, J18, J20 | Pin-headers (2 pins, 100 mil) for control signals of Raspberry Pi camera. |
|
J19, J21 | Pin-headers (2 pins, 100 mil) for control signals of “MIPI/DSI-TX to HDMI” daughter board of FORLINX EMBEDDED. |
|
J22 | Plug a jumper in J22 to turn on power of SPI-NOR / SPI-NAND (X2) flash forcibly. | No connect by default |
J23 | Plug a jumper in J23 to turn on power of SPI-NAND (X1) flash forcibly. | No connect by default |
J24 ~ J37, J40, J43, J46 | Pin-headers (4 pins, 100 mil) for measuring signals conveniently. |
|
J38, J41 | Pin-headers (1 pin) of SYS_1V8 power for supplying external devices. |
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J39, J42 | Pin-headers (1 pin) of SYS_3V power for supplying external devices. |
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J44, J47 | Pin-headers (1 pin) of SYS_3V3 power for supplying external devices. |
|
J45, J48 | Pin-header (1 pin) of SYS_5V power for supplying external devices. |
|
J49 | Plug a jumper in J49 to turn on power of VBUS of USB 3.0 Type C socket forcibly. | No connect by default |
J50 | Plug a jumper in J50 to turn on power of VBUS of USB 2.0 Micro AB socket forcibly. | No connect by default |
J51 | Pin header (5 pins, 100 mil) of SAR ADC input. The pin definitions from top to bottom are GND, CH3, CH2, CH1, and CH0. |
|
J52 | Plug a jumper in J52 to turn on power of VBUS of USB 2.0 Type A socket forcibly. | No connect by default |
J53 | Plug a jumper in J53 to turn on power of SD card forcibly. | No connect by default |
J54 | Pin-header (8 pins, 100 mil) for measuring signals of SD card. |
|
J55 | Pin header (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of GPIO50 ~ GPIO59. | Refer to Section 5. |
J60 | Pin header (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of GPIO60 ~ GPIO69. | Refer to Section 5. |
J64 | Pin header (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of GPIO70 ~ GPIO79. | Refer to Section 5. |
J56, J61 | Pin headers (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of boot devices. | Refer to Section 3. |
J73 | Pin header (2 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of boot devices. | Refer to Section 3. |
J57 | Plug a jumper in J57 to activate PER_RESET signal. | Plug a jumper in |
J58, J59, J62, J63, J65 ~ J72 | Pin headers (4 pins, 100 mil) of 1.8V / 3.3V bi-directional voltage translators. | Refer to Section 12. |
J74 | Pin-header (7 pins, 100 mil) for measuring signals of boot configuration switches (SW2 and SW3). |
|
J75 | Plug a jumper in J75 to supply power for burning OTP. | Plug a jumper in J75 when burning OTP. |
J76 | Pin header (2 pins, 100 mil) for using the signals. |
|
J77 | Pin header (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of VDDIO of AP6256. Please refer to Section 6. | Select SYS_1V8 |
J78 | Plug a jumper in J78 to turn on power of AP6256 module forcibly. | No connect by default |
3. Boot Devices and Configuration
The C3V-W chip supports booting from SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, and SD card. It supports both 1.8V and 3.0V (3.3V) IO voltage for all boot devices.
Please note:
SPI-NAND flash, 8-bit NAND flash and eMMC share pins and cannot be used at the same time (the three chips cannot be mounted on the EVB at the same time).
Please confirm the voltage of chip power supply and configure jumpers correctly. Incorrectly configuring voltage of the chip power supply will cause the chip to burn out.
The following describes configuration method of each boot device.
3.1 Boot from SPI-NOR Flash
3.1.1 Setup Switches of Boot Configuration
Boot configuration switches (SW2/SW3) are configured as shown below (SW2[1:4] = 1111, SW3[1:4] = 1011):
3.1.2 Install SPI-NOR Flash
Please insert the daughter board of SPI-NOR flash chip into the U19 position (DIP-8 socket), as shown below:
3.1.3 Setup Jumpers of Voltage Configuration
Voltage configuration jumpers are as the following table:
Supply voltage of SPI-NOR flash chip | J56 | J73 |
1.8V |  |  |
3.0V |  |  |
3.2 Boot from SPI-NAND Flash
C3V-W supports two boot positions for SPI-NAND flash chip. They are U21 (SPI_NAND_X1) and U19 (SPI_NAND_X2). The configuration method is as follows:
3.2.1 Setup Switches of Boot Configuration
Boot configuration switches (SW2/SW3) are configured as shown below (SW2[1:4] = 1111, SW3[1:4] = 1110):
3.2.2 Install SPI-NAND Flash
If you want to use the first (X1) position to boot, please insert the daughter board of SPI-NAND flash chip into the U21 (SPI_NAND_X1) position (DIP-8 socket), as shown below:
3.2.3 Mount Resistors
C3V-W EVB does not use SPI-NAND flash chip by default. To use SPI-NAND flash chip, please solder 0Ω resistors at the R405 ~ R410 positions.
3.2.4 Setup Jumpers of Voltage Configuration
Voltage configuration jumpers are as the following table for U21 (SPI_NAND_X1) position:
Supply voltage of SPI-NAND flash chip | J61 | J73 |
1.8V |  | |
3.0V |  | |
3.2.5 Install SPI-NAND Flash
If you want to use the second (X2) position to boot, please insert the daughter board of SPI-NAND flash chip into the U19 (SPI_NAND_X2) position (DIP-8 socket), as shown below:
3.2.6 Setup Jumpers of Voltage Configuration
Voltage configuration jumpers are as the following table for U19 (SPI_NAND_X2) position:
Supply voltage of SPI-NAND flash chip | J56 | J73 |
1.8V | | |
3.0V | | |
3.3 Boot from 8-bit NAND Flash
3.3.1 Mount Resistors
By default, C3V-W EVB does not use 8-bit NAND flash. To use 8-bit NAND flash, please solder 0Ω resistors at positions R382, R384, R386, R388, R390 ~ R399, R405 ~ R410.
3.3.2 Setup Switches of Boot Configuration
Boot configuration switches (SW2/SW3) are configured as shown below (SW2[1:4] = 1111, SW3[1:4] = 1000):
3.3.3 Install Daughter Board of 8-bit NAND Flash
Please insert the daughter board of 8-bit NAND flash into the U23 position (DIP-24/600mil socket), as shown below:
3.3.4 Setup Jumpers of Voltage Configuration
Voltage configuration jumpers are as the following table:
Supply voltage of 8-bit NAND flash chip | Jumper J56 and J61 | Jumper J73 |
1.8V |  | |
3.0V |  | |
3.4 Boot from eMMC Device
3.4.1 Setup Switches of Boot Configuration
Boot configuration switches (SW2/SW3) are configured as shown below (SW2[1:4] = 1111, SW3[1:4] = 1111):
3.4.2 Install Daughter board of eMMC
Please insert the daughter board of eMMC chip into the U27 position (DIP-24/600mil socket), as shown below:
3.4.3 Setup Jumpers of Voltage Configuration
Voltage configuration jumpers are as the following table:
Supply IO voltage of eMMC chip | Jumper J61 | Jumper J73 |
1.8V | | |
3.0V | | |
3.4.4 Use On-board eMMC Pads
By default, C3V-W EVB uses the daughter board of eMMC chip. If you do not use the eMMC daughter board, but directly solder the FBGA packaged eMMC chip on the EVB board. Please solder 51kΩ resistors at R258, R261, R262, R266, R268, R270, R275, R276, R277, R278 positions.
3.5 Boot from SD Card
3.5.1 Setup Switches of Boot Configuration
Boot configuration switches (SW2/SW3) are configured as shown below (SW2[1:4] = 1111, SW3[1:4] = 1100):
3.5.2 Insert SD Card
Please insert the SD card into the socket of Micro SD card, as shown below:
3.6 Boot Configuration Switches
The overall table of boot configuration switches (SW2/SW3) is as follows:
Boot devices | DIP-SW2 | DIP-SW3 | ||||||
1 | 2 | 3 | 4 | 1 | 2 | 3 | 4 | |
eMMC boot | x | x | 1 | x | 1 | 1 | 1 | 1 |
SPI-NAND boot | x | x | 1 | x | 1 | 1 | 1 | 0 |
USB boot/isp | x | x | 1 | x | 1 | 1 | 0 | 1 |
SDC boot/isp | x | x | 1 | x | 1 | 1 | 0 | 0 |
SPI-NOR boot | x | x | 1 | x | 1 | 0 | 1 | 1 |
8-bit NAND | x | x | 1 | x | 1 | 0 | 0 | 0 |
External boot | x | x | 1 | x | 0 | x | x | x |
“1” means switch OFF while “0” means switch ON. “x” means don’t care.
External boot means don’t use i-boot (internal ROM code), but external SPI-NOR to boot.
4. In-System Program (ISP)
The C3V-W chip supports in-system (on-board) program of boot devices such as SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, and eMMC. Users can save the compiled image file (ISPBOOOT.BIN) to an SD card or USB flash drive and burn it directly to the boot devices. The burning procedure is as follows.
4.1 ISP from SD Card
4.1.1 Setup Switches of Boot Configuration
Boot configuration switches (SW2/SW3) are configured as shown below (SW2[1:4] = 1111, SW3[1:4] = 1100):
4.1.2 Copy the ISPBOOOT.BIN File
Copy your ISPBOOOT.BIN (ISP image file) into an SD card and then insert it into the socket of Micro SD card, as shown below:
4.1.3 Start to ISP
Turn on the power, and the system will automatically burn the images in ISPBOOOT.BIN into the boot device.
Please note that which boot device (SPI-NOR/SPI-NAND/8-bit NAND/eMMC) is burned into is determined by the U-Boot scripts in ISPBOOOT.BIN.
4.2 ISP from USB Flash Drive
4.2.1 Setup Switches of Boot Configuration
Boot configuration switches (SW2/SW3) are configured as shown below (SW2[1:4] = 1111, SW3[1:4] = 1101):
4.2.2 Copy the ISPBOOOT.BIN File
Copy your ISPBOOOT.BIN (ISP image file) into an USB flash drive and then insert it into the CON13 (Type A), CON11 (Micro AB) or CON12 (Type C) socket.
4.2.3 Start to ISP
Turn on the power, and the system will automatically burn the images in ISPBOOOT.BIN into the boot device.
Please note that which boot device (SPI-NOR/SPI-NAND/8-bit NAND/eMMC) is burned into is determined by the U-Boot scripts in ISPBOOOT.BIN.
5. Configure Voltage of GPIO (also known as DVIO)
GPIO50 (AO_MX0) ~ GPIO79 (AO_MX29) support 1.8V and 3.0V dual operation voltage. They are divided into three groups:
VDD_DVIO_AO_1 Group: GPIO50 (AO_MX0) ~ GPIO59 (AO_MX9)
VDD_DVIO_AO_2 Group: GPIO60 (AO_MX10) ~ GPIO69 (AO_MX19)
VDD_DVIO_AO_3 Group: GPIO70 (AO_MX20) ~ GPIO79 (AO_MX29)
GPIO20 (G_MX20) ~ GPIO37 (G_MX37) can also be used as GPIO when not used as boot device pins. They support 1.8V and 3.0V dual operation voltage and are divided into two groups:
VDD_DVIO_1 Group: GPIO21 (G_MX21) ~ GPIO27 (G_MX27)
VDD_DVIO_2 Group: GPIO20 (G_MX20), GPIO28 (G_MX28) ~ GPIO37 (G_MX37)
Each group can be configured separately. The configuration method is as follows.
5.1 Configure Voltage of VDD_DVIO_AO_1 Group
Voltage of VDD_DVIO_AO_1 group is configured by jumper J55.
Voltage of VDD_DVIO_AO_1 | J55 |
1.8V |  |
3.0V |  |
5.2 Configure Voltage of VDD_DVIOAO_2 Goup
Voltage of VDD_DVIO_AO_2 group is configured by jumper J60.
Voltage of VDD_DVIO_AO_2 | J60 |
1.8V |  |
3.0V |  |
5.3 Configure Voltage of VDD_DVIO_AO_3 Group
Voltage of VDD_DVIO_AO_3 is configured by jumper J64.
Voltage of VDD_DVIO_AO_3 | J64 |
1.8V |  |
3.0V |  |
5.4 Configure Voltage of VDD_DVIO_1 Group
Voltage of VDD_DVIO_1 is configured by jumper J56.
Voltage of VDD_DVIO_1 | J56 |
1.8V |  |
3.0V |  |
5.5 Configure Voltage of VDD_DVIO_2 Group
Voltage of VDD_DVIO_2 is configured by jumper J61
Voltage of VDD_DVIO_2 | J61 |
1.8V |  |
3.0V |  |
5.6 Additional Note
Please note that for GPIOs that support dual operation voltage of 1.8V and 3.0V, in addition to configuring the power supply in the hardware, the software also needs to set the MS control bit to get the correct bias voltage.
i-boot will set MS control bit for boot devices if you set jumper J73 correctly.
6. Configure VDDIO Voltage of AP6256 (WiFi/Bluetooth)
Please configure VDDIO voltage of AP6256 as SYS_1V8. The AP6256 IO voltage configuration method is as follows:
| J77 |
SYS_1V8 |  |
VDD_DVIO_SDIO |  |
7. CA55 JTAG ICE
7.1 Mount Resistors
Note that, by default, C3V-W EVB does not use the CA55 JTAG interface. To use the CA55 JTAG interface, please solder the 2x10 pin-header at the CON8 position. Solder the 0Ω resistor at the R400 ~ R404 position. Remove the 0Ω resistor at the R348 ~ R352 position.
7.2 Enable CA55 JTAG Interface
To enable the CA55 JTAG interface, configure the boot configuration switch SW2 as shown below (SW2[1:4] = 1110):
7.3 Setup Swithes of Boot Configuration
Configure the boot configuration switch SW3 for boot devices. For example, if you want to boot from eMMC, configure it as follows (SW3[1:4] = 1111):
7.4 Install JTAG Cable
Connect the JTAG cable of CA55 ICE to CON8 as shown below:
7.5 Additional Note
Please refer to Appendix 1 for pin definitions of pin-header of CA55 JTAG interface and wiring.
8. CM4 JTAG ICE
8.1 Mount Resistors
Note that, by default, C3V-W EVB does not use the CM4 JTAG interface. To use the CM4 JTAG interface, please solder the 2x10 pin-header at the CON9 position. Solder 0Ω resistors at the R379, R384, R381, R383, R387, and R389 positions. Remove R364, R365, 0Ω resistors at R367, R369, and R370 positions.
8.2 Install JTAG Cable
Connect the JTAG cable of CM4 ICE to CON9 as shown below:
8.3 Setup Registers
By default, CM4 JTAG interface is disabled. To enable it, please set CFG_CM4_JTAG_SEL (0xf8800094[0]) to 1 and MO_CM4_DBGEN (0xf880024c[2]) to 1 in x-boot or U-Boot.
8.4 Additional Note
Please refer to Appendix 10 for Pin definitions of pin-header of CM4 JTAG interface and wiring.
9. Connect to TP2815 Daughter Board
TP2815 converts 4 car HD camera into a MIPI/CSI-TX output (with 4 data lanes and 4 virtual channels). TP2815 daughter board is used to test virtual channel functions of MIPI/CSI-RX2/3/4/5.
9.1 Connect TP2815 Daughter Board
As shown in the figure below, the MIPI-RX5 of C3V-W EVB is connected to the TP2815 daughter board via a FFC cable.
Do not connect the DC JACK JK1 of the TP2815 daughter board to the +12V power supply. The power supply of TP2815 daughter board is supplied by C3V-W EVB directly.
9.2 Setup J1
As shown below, choose 5V for J1 (right side) of TP2815 daughter board.
9.3 Setup J2
As shown below, choose 3.3V for J2 (right side) of TP2815 daughter board.
9.4 Connect Camera
Connect CN1, CN2, CN3 and CN4 to car HD camera (ex: Rec Technology FM-531).
10. Connect to Daughter Board of MIPI/DSI to HDMI of Forlinx Embedded
The daughter board of “MIPI/DSI to HDMI” of Forlinx Embedded is used to convert MIPI/DSI-TX output to HDMI output. The main chip of the daughter board is Lontium LT8912B. With HDMI display output, you can connect display output of EVB to any HDMI LCD monitor.
11. CPIO and MIPI/CSI-RX2/3
CPIO is a high-speed (4.8 GB/s) interface for connecting to peripheral chips. Chip-to-chip (external mode, on board) transfers support a maximum speed of 4.8 GB/s, and die-to-die (internal mode, in package) transfers support a maximum speed of 9.6 GB/s. Refer to picture below, Samtec differential socket is used for CPIO interface:
The part number of CPIO socket is QSH-020-01-F-D-DP (socket). If you design a daughter board to connect to EVB via the CPIO, please use the Samtec QTH-020-0x-F-D-DP terminal (where x is 1, 2, 3, …). If you want to connect the CPIO to other boards via cables, please use Samtec differential cables, part number HQDP-020-06.00-TEU-TED-5 for crossover mode or HQDP-020-06.00-TEU-TEU-8 for swap mode (where 06.00 is length of cable).
Besides, two channels MIPI/CSI-RX (MIPI/CSI-RX2 and MIPI/CSI-RX3) interfaces share the same pins of CPIO. If CPIO functionality is not required, two channels MIPI/CSI-RX can be enabled. Refer to pin definitions of MIPI/CSI-RX2 and MIPI/CSI-RX3 below. MIPI/CSI-RX2 supports up to 4 data lanes while MIPI/CSI-RX3 supports up to 2 data lanes.
Please refer to Appendix 8 for pin definitions of Samtec differential socket of CPIO.
12. 1.8V — 3.3V/3.0V Bi-directional Voltage Translator
C3V-W EVB supports 1 set (8 bits) AO_1V8 / AO_3V bi-directional voltage translator and 2 sets (16 bits) SYS_1V8 / SYS_3V3 bi-directional voltage translators.
12.1 Pin-headers (4 pins, 100 mil) of the Bi-directional Voltage Translators
12.2 Schematics of AO_1V8 / AO_3V Bi-directional Voltage Translators
12.3 Schematics of SYS_1V8 / SYS_3V3 Bi-directional Voltage Translators
13. Appendix
13.1 Pin Definition of Pin-header (10x2 pins, 100 mil) of CA55 JTAG Interface and Wiring
13.2 Pin Definition of Daughter Board of eMMC
13.3 Pin Definition of Daughter Board of 8-bit NAND Flash
13.4 Pin Definition of Pin-header (10x2 pins, 100 mil) of Audio
13.5 Pin Definition of FFC Connector (15 pins, 1.0mm) of MIPI-RX4 and Wiring
13.6 Pin Definition of FFC Connector (15 pins, 1.0mm) of MIPI-RX5 and Wiring
13.7 Pin Definition of 15-pin FFC Connector (15pins, 1.0mm, 1c2d) and 30-pin FFC Connector (30 pins, 0.5mm, 1c4d) of MIPI-TX and Wiring
13.8 Pin Definition of Samtec Differential Socket of CPIO and Wiring
13.9 Pin Definition of Pin-header (10x2, 100 mil) of CM4 JTAG Interface and Wiring
