本实验以Plus1 7021实践平台配套的FPGA子板和扩展测试子板完成相关实验，FPGA子板的开发工具采用XILINX的Vivado集成开发环境(版本号为2018.3);为了方便将用户自己需要验证的IP方便连接到SOC系统中验证，本实验提供了相应的基础文件，如下
5.6.1 Vivado 软件的安装
请用户自行安装Xilinx Vivado 2018.3以上版本；本实验使用Vivado 2018.3版本,安装完成后桌面出现如下图标
5.6.2 FPGA实验项目的加载
双击Vivado图标开始运行,出现如下界面：
点击红框Open Project, 选择led_7segment_ctl/led目录下的led.xpr,出现如下界面
完成项目的加载过程，如下
上图红框的Preject Manager 实现项目的设置，包含源码的添加及修改等
5.6.3 FPGA 实验项目的时钟设置
本实验所用FPGA子板的输入时钟有两路：
一路是FPGA板上自带的25M时钟GCLK, 在fpga_top.xdc约束文件里有相关约束：
create_clock -period 40.000 -name GCLK -waveform {0.000 20.000} [get_ports GCLK]
接入FPGA后利用其内部自带的PLL IP, 产生项目所需的FBIO TX时钟io_clk，参考时钟ref_clk及系统时钟sysclk；对应的源码文件架构如下
另一路是FBIO BUS接入FPGA的FBIO RX 36M时钟；在fpga_top.xdc约束文件里有相关约束：
create_clock -period 27.000 -name rclk -waveform {0.000 12.500} [get_ports {FPGA_PAD[35]}]
下面介绍GCLK接入FPGA后利用其内部自带的PLL IP, 产生项目所需的时钟, 参考下图，双击红框，启动PLL 设置操作
5.6.3.1 输入时钟设置
如下图所示，PLL的输入时钟来自FPGA子板上的25M时钟
5.6.3.2 输出时钟设置：
PLL输出项目所需的三个时钟，介绍如下：
clk_out1/clk_out2 为FBIO 模组所需，其中本实验中clk_out1为36M,用户可通过修改的设置来改变FBIO TX/RX的传输速度；
clk_out3 为FPGA 子板运行的系统时钟65M；
5.6.4 FPGA 实验项目的复位设置
通过FBIO BUS,将来自SP7021 CPU 产生的reset信号接入FPGA的 FPGA_PAD[18];
aim_reset_sync.v 模块进行同步化处理后产生FPGA系统所需的复位信号sysrstn，对应的源码文件架构如下
5.6.5 FPGA 实验项目的约束文件设置
为使设计的时序满足要求，需要对设计进行时序相关的约束，对应的源码文件架构如下
分析fpga_top.xdc如下：
FPGA 输入时钟输入约束
#FPGA clock input
create_clock -period 40.000 -name GCLK -waveform {0.000 20.000} [get_ports GCLK]
create_clock -period 27.000 -name rclk -waveform {0.000 12.500} [get_ports {FPGA_PAD[35]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets FPGA_PAD_IOBUF[35]_inst/O]
FPGA 系统管脚分配
#FPGA_PADs connection for system
set_property PACKAGE_PIN P17 [get_ports GCLK]
set_property PACKAGE_PIN T8 [get_ports {FPGA_PAD[0]}]
set_property PACKAGE_PIN V9 [get_ports {FPGA_PAD[1]}]
set_property PACKAGE_PIN N6 [get_ports {FPGA_PAD[2]}]
set_property PACKAGE_PIN U6 [get_ports {FPGA_PAD[3]}]
set_property PACKAGE_PIN V6 [get_ports {FPGA_PAD[4]}]
set_property PACKAGE_PIN T6 [get_ports {FPGA_PAD[5]}]
set_property PACKAGE_PIN V4 [get_ports {FPGA_PAD[6]}]
set_property PACKAGE_PIN R6 [get_ports {FPGA_PAD[7]}]
set_property PACKAGE_PIN U4 [get_ports {FPGA_PAD[8]}]
set_property PACKAGE_PIN V2 [get_ports {FPGA_PAD[9]}]
set_property PACKAGE_PIN V1 [get_ports {FPGA_PAD[10]}]
set_property PACKAGE_PIN N5 [get_ports {FPGA_PAD[11]}]
set_property PACKAGE_PIN T5 [get_ports {FPGA_PAD[12]}]
set_property PACKAGE_PIN T3 [get_ports {FPGA_PAD[13]}]
set_property PACKAGE_PIN N4 [get_ports {FPGA_PAD[14]}]
set_property PACKAGE_PIN T1 [get_ports {FPGA_PAD[15]}]
set_property PACKAGE_PIN R2 [get_ports {FPGA_PAD[16]}]
set_property PACKAGE_PIN N1 [get_ports {FPGA_PAD[17]}]
set_property PACKAGE_PIN M1 [get_ports {FPGA_PAD[18]}]
set_property PACKAGE_PIN M3 [get_ports {FPGA_PAD[19]}]
set_property PACKAGE_PIN M2 [get_ports {FPGA_PAD[20]}]
set_property PACKAGE_PIN D8 [get_ports {FPGA_PAD[21]}]
set_property PACKAGE_PIN C7 [get_ports {FPGA_PAD[22]}]
set_property PACKAGE_PIN L1 [get_ports {FPGA_PAD[23]}]
set_property PACKAGE_PIN N2 [get_ports {FPGA_PAD[24]}]
set_property PACKAGE_PIN P2 [get_ports {FPGA_PAD[25]}]
set_property PACKAGE_PIN R1 [get_ports {FPGA_PAD[26]}]
set_property PACKAGE_PIN M4 [get_ports {FPGA_PAD[27]}]
set_property PACKAGE_PIN P3 [get_ports {FPGA_PAD[28]}]
set_property PACKAGE_PIN P4 [get_ports {FPGA_PAD[29]}]
set_property PACKAGE_PIN R3 [get_ports {FPGA_PAD[30]}]
set_property PACKAGE_PIN T4 [get_ports {FPGA_PAD[31]}]
set_property PACKAGE_PIN P5 [get_ports {FPGA_PAD[32]}]
set_property PACKAGE_PIN U1 [get_ports {FPGA_PAD[33]}]
set_property PACKAGE_PIN U2 [get_ports {FPGA_PAD[34]}]
set_property PACKAGE_PIN U3 [get_ports {FPGA_PAD[35]}]
set_property PACKAGE_PIN R5 [get_ports {FPGA_PAD[36]}]
set_property PACKAGE_PIN V5 [get_ports {FPGA_PAD[37]}]
set_property PACKAGE_PIN R7 [get_ports {FPGA_PAD[38]}]
set_property PACKAGE_PIN V7 [get_ports {FPGA_PAD[39]}]
set_property PACKAGE_PIN U7 [get_ports {FPGA_PAD[40]}]
set_property PACKAGE_PIN M6 [get_ports {FPGA_PAD[41]}]
set_property PACKAGE_PIN U9 [get_ports {FPGA_PAD[42]}]
set_property PACKAGE_PIN R8 [get_ports {FPGA_PAD[43]}]
set_property IOSTANDARD LVCMOS33 [get_ports FPGA_PAD*]
set_property IOSTANDARD LVCMOS33 [get_ports GCLK]
set_property PULLDOWN true [get_ports {FPGA_PAD[18]}]
set_property SLEW FAST [get_ports FPGA_PAD*]
FPGA 项目时序例外的约束
#Timing exception set
set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *clk_out1*]
set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *clk_out3*]
set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *clk_out2*]
set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *clk_out3*]
set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *clk_out2*]
set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *clk_out1*]
set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *rclk*]
set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out2*]
set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *rclk*]
set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out3*]
set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out1*]
set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *rclk*]
set_false_path -from [get_ports *FPGA_PAD[18]*] -to [all_registers]
set_false_path -from [all_registers] -to [get_ports *FPGA_PAD[19]*]
set_false_path -from [all_registers] -to [get_ports *FPGA_PAD[23]*]
set_max_delay -from [all_registers -edge_triggered] -through [get_nets *FPGA_PAD*] -to [all_outputs] 6.000
set_max_delay -from [all_inputs] -through [get_nets *FPGA_PAD*] -to [all_registers -edge_triggered] 4.000
FPGA 用户IP管脚分配
#FPGA_LEDs connection for user IP
set_property PACKAGE_PIN B6 [get_ports {FPGA_LED[0]}]
set_property PACKAGE_PIN A5 [get_ports {FPGA_LED[1]}]
set_property PACKAGE_PIN C5 [get_ports {FPGA_LED[2]}]
set_property PACKAGE_PIN B4 [get_ports {FPGA_LED[3]}]
set_property PACKAGE_PIN B7 [get_ports {FPGA_LED[4]}]
set_property PACKAGE_PIN A6 [get_ports {FPGA_LED[5]}]
set_property PACKAGE_PIN C6 [get_ports {FPGA_LED[6]}]
set_property PACKAGE_PIN C4 [get_ports {FPGA_LED[7]}]
set_property PACKAGE_PIN A3 [get_ports {FPGA_LED[8]}]
set_property PACKAGE_PIN A4 [get_ports {FPGA_LED[9]}]
set_property PACKAGE_PIN D4 [get_ports {FPGA_LED[10]}]
set_property PACKAGE_PIN D5 [get_ports {FPGA_LED[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports FPGA_LED*]
FPGA 编程相关配置，用户不需要修改
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
5.6.6 FPGA实验项目的实现
上图的3个红框依次运行，完成项目的综合，布局布线的实现以及烧录文件的生成
5.6.7 FPGA实验项目的下载
项目烧录文件生成后，需要下载到FPGA子板上测试，为此需要准备号下载工具与开发板的连接；下图将Xilinx通用的JTAG下载器按图信号连接到fpga子板
接下来开始FPGA 代码的下载，下面分两种下载方式说明，如下图
首先按左图红框所示顺序启动下载，得到右图所示Hardware 界面
1) FPGA 代码到下载到内部的SRAM
可实现在线运行及调试，掉电后需要重新下载
点击红框Program Device下载FPGA 代码到SRAM
点击红框Program Device完成下载
2) FPGA 代码到下载到外部的Flash
当用户的FPGA代码调试完毕需要固化到板上的Flash时，进行如下操作
点击红框Add Configuration Memory Device 开始固化FPGA 代码到板上Flash，如下：
点击OK,出现如下配置文件加载
点击OK开始对配置SPI Flash 进行编程
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