5.6 Development and implementation of FPGA experiment project

This experiment uses the FPGA daughter board and extended test daughter board supporting the Plus1 7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses the XILINX Vivado integrated development environment (version number 2018.3); in order to facilitate the user to verify the IP It is convenient to connect to the SOC system for verification. This experiment provides the corresponding basic files, as follows

5.6.1 Vivado software installation

Please install Xilinx Vivado 2018.3 or above by yourself; this experiment uses Vivado 2018.3 version. After installation, the following icon appears on the desktop

5.6.2 FPGA experiment project loading

Double-click the Vivado icon to start running, the following interface appears:

Click the red box Open Project, select led.xpr under led_7segment_ctl/led directory, the following interface appears

Complete the loading process of the project, as follows

The Project Manager in the red box above implements the project settings, including the addition and modification of source code, etc.

5.6.3 FPGA experiment project clock setting

There are two input clocks for the FPGA daughter board used in this experiment: All the way is the 25M clock GCLK that comes with the FPGA board. There are relevant constraints in the fpga_top.xdc constraint file: create_clock -period 40.000 -name GCLK -waveform {0.000 20.000} [get_ports GCLK] After accessing FPGA, use its internal PLL IP to generate the FBIO TX clock io_clk, reference clock ref_clk and system clock sysclk required by the project; the corresponding source file structure is as follows

The other way is the FBIO RX 36M clock of the FBIO BUS connected to the FPGA; there are related constraints in the fpga_top.xdc constraint file: create_clock -period 27.000 -name rclk -waveform {0.000 12.500} [get_ports {FPGA_PAD [35]}] The following introduces the use of its internal PLL IP after GCLK is connected to the FPGA to generate the clock required by the project. Refer to the figure below, double-click the red box to start the PLL setting operation

5.6.3.1 Input clock settings

As shown in the figure below, the PLL input clock comes from the 25M clock on the FPGA daughter board

5.6.3.2 Output clock setting

The three clocks required for the PLL output project are described as follows: clk_out1 / clk_out2 is required for the FBIO module. In this experiment, clk_out1 is 36M. The user can change the transmission speed of FBIO TX / RX by modifying the settings; clk_out3 is the system clock 65M running on the FPGA daughter board;

5.6.4 Reset settings of FPGA experiment project

Through FBIO BUS, connect the reset signal generated from SP7021 CPU to FPGA FPGA_PAD [18]; The aim_reset_sync.v module performs synchronization processing to generate the reset signal sysrstn required by the FPGA system. The corresponding source file structure is as follows

5.6.5 Constraint file setting for FPGA experiment project

In order to make the timing of the design meet the requirements, it is necessary to carry out timing-related constraints on the design. The corresponding source file structure is as follows

Analysis of fpga_top.xdc is as follows:

FPGA input clock input constraints

#FPGA clock input

create_clock -period 40.000 -name GCLK -waveform {0.000 20.000} [get_ports GCLK]

create_clock -period 27.000 -name rclk -waveform {0.000 12.500} [get_ports {FPGA_PAD[35]}]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets FPGA_PAD_IOBUF[35]_inst/O]

FPGA system pin assignment

#FPGA_PADs connection for system

set_property PACKAGE_PIN P17 [get_ports GCLK]

set_property PACKAGE_PIN T8 [get_ports {FPGA_PAD[0]}]

set_property PACKAGE_PIN V9 [get_ports {FPGA_PAD[1]}]

set_property PACKAGE_PIN N6 [get_ports {FPGA_PAD[2]}]

set_property PACKAGE_PIN U6 [get_ports {FPGA_PAD[3]}]

set_property PACKAGE_PIN V6 [get_ports {FPGA_PAD[4]}]

set_property PACKAGE_PIN T6 [get_ports {FPGA_PAD[5]}]

set_property PACKAGE_PIN V4 [get_ports {FPGA_PAD[6]}]

set_property PACKAGE_PIN R6 [get_ports {FPGA_PAD[7]}]

set_property PACKAGE_PIN U4 [get_ports {FPGA_PAD[8]}]

set_property PACKAGE_PIN V2 [get_ports {FPGA_PAD[9]}]

set_property PACKAGE_PIN V1 [get_ports {FPGA_PAD[10]}]

set_property PACKAGE_PIN N5 [get_ports {FPGA_PAD[11]}]

set_property PACKAGE_PIN T5 [get_ports {FPGA_PAD[12]}]

set_property PACKAGE_PIN T3 [get_ports {FPGA_PAD[13]}]

set_property PACKAGE_PIN N4 [get_ports {FPGA_PAD[14]}]

set_property PACKAGE_PIN T1 [get_ports {FPGA_PAD[15]}]

set_property PACKAGE_PIN R2 [get_ports {FPGA_PAD[16]}]

set_property PACKAGE_PIN N1 [get_ports {FPGA_PAD[17]}]

set_property PACKAGE_PIN M1 [get_ports {FPGA_PAD[18]}]

set_property PACKAGE_PIN M3 [get_ports {FPGA_PAD[19]}]

set_property PACKAGE_PIN M2 [get_ports {FPGA_PAD[20]}]

set_property PACKAGE_PIN D8 [get_ports {FPGA_PAD[21]}]

set_property PACKAGE_PIN C7 [get_ports {FPGA_PAD[22]}]

set_property PACKAGE_PIN L1 [get_ports {FPGA_PAD[23]}]

set_property PACKAGE_PIN N2 [get_ports {FPGA_PAD[24]}]

set_property PACKAGE_PIN P2 [get_ports {FPGA_PAD[25]}]

set_property PACKAGE_PIN R1 [get_ports {FPGA_PAD[26]}]

set_property PACKAGE_PIN M4 [get_ports {FPGA_PAD[27]}]

set_property PACKAGE_PIN P3 [get_ports {FPGA_PAD[28]}]

set_property PACKAGE_PIN P4 [get_ports {FPGA_PAD[29]}]

set_property PACKAGE_PIN R3 [get_ports {FPGA_PAD[30]}]

set_property PACKAGE_PIN T4 [get_ports {FPGA_PAD[31]}]

set_property PACKAGE_PIN P5 [get_ports {FPGA_PAD[32]}]

set_property PACKAGE_PIN U1 [get_ports {FPGA_PAD[33]}]

set_property PACKAGE_PIN U2 [get_ports {FPGA_PAD[34]}]

set_property PACKAGE_PIN U3 [get_ports {FPGA_PAD[35]}]

set_property PACKAGE_PIN R5 [get_ports {FPGA_PAD[36]}]

set_property PACKAGE_PIN V5 [get_ports {FPGA_PAD[37]}]

set_property PACKAGE_PIN R7 [get_ports {FPGA_PAD[38]}]

set_property PACKAGE_PIN V7 [get_ports {FPGA_PAD[39]}]

set_property PACKAGE_PIN U7 [get_ports {FPGA_PAD[40]}]

set_property PACKAGE_PIN M6 [get_ports {FPGA_PAD[41]}]

set_property PACKAGE_PIN U9 [get_ports {FPGA_PAD[42]}]

set_property PACKAGE_PIN R8 [get_ports {FPGA_PAD[43]}]

set_property IOSTANDARD LVCMOS33 [get_ports FPGA_PAD*]

set_property IOSTANDARD LVCMOS33 [get_ports GCLK]

set_property PULLDOWN true [get_ports {FPGA_PAD[18]}]

set_property SLEW FAST [get_ports FPGA_PAD*]

FPGA project timing exception constraints

#Timing exception set

set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *clk_out1*]

set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *clk_out3*]

set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *clk_out2*]

set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *clk_out3*]

set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *clk_out2*]

set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *clk_out1*]

set_false_path -from [get_clocks *clk_out2*] -to [get_clocks *rclk*]

set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out2*]

set_false_path -from [get_clocks *clk_out3*] -to [get_clocks *rclk*]

set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out3*]

set_false_path -from [get_clocks *rclk*] -to [get_clocks *clk_out1*]

set_false_path -from [get_clocks *clk_out1*] -to [get_clocks *rclk*]

set_false_path -from [get_ports *FPGA_PAD[18]*] -to [all_registers]

set_false_path -from [all_registers] -to [get_ports *FPGA_PAD[19]*]

set_false_path -from [all_registers] -to [get_ports *FPGA_PAD[23]*]

set_max_delay -from [all_registers -edge_triggered] -through [get_nets *FPGA_PAD*] -to [all_outputs] 6.000

set_max_delay -from [all_inputs] -through [get_nets *FPGA_PAD*] -to [all_registers -edge_triggered] 4.000

FPGA user IP pin assignment

#FPGA_LEDs connection for user IP

set_property PACKAGE_PIN B6 [get_ports {FPGA_LED[0]}]

set_property PACKAGE_PIN A5 [get_ports {FPGA_LED[1]}]

set_property PACKAGE_PIN C5 [get_ports {FPGA_LED[2]}]

set_property PACKAGE_PIN B4 [get_ports {FPGA_LED[3]}]

set_property PACKAGE_PIN B7 [get_ports {FPGA_LED[4]}]

set_property PACKAGE_PIN A6 [get_ports {FPGA_LED[5]}]

set_property PACKAGE_PIN C6 [get_ports {FPGA_LED[6]}]

set_property PACKAGE_PIN C4 [get_ports {FPGA_LED[7]}]

set_property PACKAGE_PIN A3 [get_ports {FPGA_LED[8]}]

set_property PACKAGE_PIN A4 [get_ports {FPGA_LED[9]}]

set_property PACKAGE_PIN D4 [get_ports {FPGA_LED[10]}]

set_property PACKAGE_PIN D5 [get_ports {FPGA_LED[11]}]

set_property IOSTANDARD LVCMOS33 [get_ports FPGA_LED*]

Note:FPGA programing related configure information，do not modify

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]

set_property CONFIG_VOLTAGE 1.8 [current_design]

set_property CFGBVS GND [current_design]

set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]

set_property CONFIG_MODE SPIx4 [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

5.6.6 Implementation of FPGA experiment project

The three red boxes in the above figure run in sequence to complete the synthesis of the project, the implementation of layout and wiring, and the generation of the burning file

5.6.7 FPGA experiment project download

After the project burning file is generated, it needs to be downloaded to the FPGA daughter board for testing. To this end, you need to prepare the connection between the download tool and the development board; the following figure connects the Xilinx universal JTAG downloader to the fpga daughter board according to the figure