This document serves as a comprehensive guide for PCB design tailored specifically for the SP7350. It supplements the application circuits provided for the SP7350. Chapter 1 outlines essential guidelines for high-speed signal routing, while Chapter 2 presents technical data or criteria for designing SP7350 PCBs.
Table of Contents
Routing high-speed signals on a PCB requires careful consideration to maintain signal integrity and minimize electromagnetic interference (EMI). Here are some guidelines for routing high-speed signals on a PCB:
Controlled Impedance:
Maintain a consistent and controlled impedance for high-speed signal traces.
Utilize PCB stack-ups with suitable dielectric materials and thicknesses to achieve the desired impedance.
Ensure trace width, spacing, and layer stack-up align with the target impedance, often set for differential pairs (e.g., 90 ohms for USB SuperSpeed).
Short and Direct Traces:
Keep high-speed signal traces as short and direct as possible to minimize signal propagation delay and reduce the risk of signal distortion.
Minimize the number of vias and avoid using stubs in the signal path to prevent reflections.
Differential Pair Routing:
Route differential pairs closely to maintain signal integrity and reduce EMI.
Ensure length matching between the positive and negative signals of a differential pair to preserve signal balance.
Avoid Sharp Bends and Right Angles:
Use gentle curves for routing high-speed signals to reduce signal reflections and EMI.
Avoid sharp bends and right angles, which can act as antennas and cause signal degradation.
Ground Plane:
Provide a continuous and solid ground plane beneath high-speed signal traces to act as a reference plane and reduce EMI.
Use stitching vias to connect multiple ground planes or ground layers together to maintain a low-impedance return path.
Signal Layer Arrangement:
Place high-speed signal traces on internal layers close to a solid ground plane to shield them from external interference.
Avoid routing high-speed signals on the outer layers of the PCB, especially near the board edges, to minimize radiation.
Decoupling Capacitors:
Place decoupling capacitors close to the power pins of high-speed ICs to provide a low-impedance path for high-frequency current and stabilize the power supply.
Use a variety of capacitor values (e.g., 1nF, 10nF, 0.1µF, 1µF) to filter out different frequency ranges of noise.
Signal Return Path:
Ensure that the signal return path (or ground path) for high-speed signals is as close as possible to the signal trace to reduce loop area and minimize inductance.
Avoid splitting the ground plane beneath high-speed signal traces, as it can lead to discontinuities and increase EMI.
Avoid Crosstalk:
Maintain adequate spacing between high-speed signal traces to minimize crosstalk.
Use ground or power plane between sensitive signals to provide isolation and reduce interference.
Simulation and Analysis:
Utilize PCB design software for simulating and analyzing signal integrity, impedance matching, and EMI issues.
Perform signal integrity analyses like eye diagrams, reflection, and crosstalk to validate and adjust the design.
Refer to: Texas Instruments' Application Report "High-Speed Layout Guidelines"
Right-angle bends in traces can lead to increased radiation due to several factors:
Increased Capacitance: The capacitance rises in the corner region of a right angle.
Impedance Variations: The characteristic impedance undergoes changes at right-angle bends, leading to signal reflections.
To mitigate these issues, it's advisable to avoid right-angle bends in traces. Instead, aim to route traces with two 45° corners or opt for a rounded bend. This approach minimizes impedance changes, reducing the risk of signal reflections and ensuring better signal integrity. As depicted in the following figures, the width of a trace increases by 40% when a right-angle bend is employed, whereas it reduces to 8% with two 45° corners. Alternatively, utilizing a rounded bend provides the most optimal solution.
Keeping the current loop as small as possible is a fundamental principle in PCB design for several reasons:
Minimize Electromagnetic Interference (EMI): A smaller current loop reduces the area enclosed by the loop, which in turn decreases the loop's magnetic field. This helps to minimize electromagnetic interference both within the circuit and with neighboring circuits, leading to better signal integrity and reduced susceptibility to noise.
Reduced Inductance: A smaller loop area corresponds to lower loop inductance. Inductance opposes changes in current flow, so minimizing it helps improve the circuit's response time and stability. This is particularly important in high-frequency circuits where even small inductances can have significant effects.
Decreased Radiated Emissions: By minimizing the size of the current loop, you also reduce the extent to which the circuit radiates electromagnetic energy. This is especially important for compliance with electromagnetic compatibility (EMC) regulations, which limit the amount of electromagnetic radiation devices can emit.
Less Crosstalk: Smaller current loops reduce the likelihood of crosstalk between adjacent signal traces. Crosstalk occurs when the magnetic field generated by one trace induces a voltage in an adjacent trace, leading to signal degradation or interference.
Overall, keeping the current loop as small as possible helps to maintain signal integrity, minimize interference, and improve the performance and reliability of the PCB design. Various techniques are employed to minimize the area of current loops.
At higher frequencies, the return current naturally seeks the path of least impedance, typically flowing beneath the ground plane. In the illustration below, the forward current (indicated by the blue arrow) travels along a trace from the signal source to its destination, while the return current (highlighted by the red arrow) follows beneath the ground plane, flowing from the sink back to the source.
However, the presence of slots or gaps in the ground plane can disrupt these currents, causing them to circumvent the slot area, as shown in the figure below.
This discontinuity in the ground plane can lead to increased loop areas and higher impedance, potentially affecting signal integrity and increasing electromagnetic interference (EMI).
Several solutions exist to address return current disruptions caused by slots in the ground reference plane. One option is to place a ground wire over the slot to provide continuity in the ground path. As illustrated in the following figure, the return current (red arrow) travels upward through a via, then along the ground trace, and finally downward through another via, ultimately reconnecting with the ground plane. This route effectively bypasses the slot area, minimizing the loop area around the slot and ensuring uninterrupted current flow.
Another approach involves routing the signal path in alignment with the flow of return currents, minimizing loop area.
Additionally, some designers employ bypass capacitors to bridge return currents flowing on other ground or power planes. This helps ensure a low-impedance path for high-frequency currents, stabilizing the power supply and minimizing noise in the circuit. By implementing these strategies, designers can mitigate the effects of return current disruptions and maintain signal integrity in high-speed PCB designs.
However, the most effective solution is to avoid incorporating slots altogether in the ground reference plane design.
The excessive presence of adjacent vias can lead to the inadvertent disruption of power or ground planes. Incorrect via placement, particularly when dealing with bus signals, can result in undesirable slots within the ground plane as depicted in the left figure below. Here, the blue arrow represents forward current on the trace, while the red arrow denotes return current beneath the ground plane. The presence of five adjacent vias creates a disruptive slot, causing the return current to deviate around this area.
To address this, relocating two vias slightly downward, as shown in the right figure below, effectively minimizes the loop area for return current. This adjustment significantly aids in mitigating potential signal integrity concerns by reducing disruptive effects.
In a differential pair, the signals on each trace are theoretically equal in magnitude but opposite in polarity. This configuration ensures that their electromagnetic fields cancel each other, effectively minimizing interference with the return current on the ground plane. To maintain this balance, it's essential for both signal traces to have equal lengths, ensuring uniform propagation delay times
Consistent width and spacing between traces in a differential pair, as illustrated in the figure below, are critical for controlling uniform impedance. A contiguous ground plane beneath the pair further bolsters signal integrity. Narrower spacing between traces enhances signal integrity. It's recommended to maintain a clearance from other traces or planes at least three times the width of the individual traces. In cases of space constraints, a minimum clearance of two times the trace width is advisable
When routing a differential pair, employing curved traces can offer several benefits, including improved signal integrity and reduced electromagnetic interference. Below is an example of routing a differential pair with curved traces:
To optimize signal integrity and minimize electromagnetic interference, it's recommended to maintain a clearance from the boundary of the ground plane that is at least three times the width of the trace. In scenarios where space is limited, a clearance of at least two times the trace width should be maintained.
In a single-ended clock net, incorporating ground traces on both sides offers an additional path for return current, effectively reducing electromagnetic interference. As depicted below, the return current traverses through both ground traces, generating opposing electromagnetic fields. This configuration, akin to a differential pair, facilitates the cancellation of a substantial portion of the electromagnetic field
It is important to note that ground vias at both ends ensure return current flows through the ground traces effectively.
When considering routing on a 6-layer PCB, the layer arrangement is crucial for optimal signal integrity. The recommended stack-up is as follows:
Layer 1 (Top): Signal routing
Layer 2 (L2_GND): Ground plane
Layer 3 (L3_S): Signal routing
Layer 4 (L4_VCC): Power plane
Layer 5 (L5_GND): Ground plane
Layer 6 (Bottom): Signal routing
Layer 1 (Top), Layer 3 (L3_S), and Layer 6 (Bottom) are designated for signal routing as they are adjacent to ground planes. These adjacent ground planes serve as paths for return current, effectively minimizing the loop area and reducing electromagnetic interference.
Layer 3 (L3_S) provides additional shielding against external electromagnetic interference, effectively reducing radiation. However, to fully leverage the benefits of this internal layer, vias are essential at both the source and sink sides of the signal path. This is because components are typically placed on the top or bottom layers of the circuit board, necessitating vias to facilitate signal transition between the internal layer and these outer layers.
It's best to route a net on the same layer to avoid impedance changes caused by vias, which can lead to reflections. If changing layers is unavoidable, transitioning between Layer 1 and Layer 3 (or vice versa) is recommended. This helps minimize the loop area and the electromagnetic field, thereby reducing the risk of interference. As depicted in the figure below, the net initially follows a path on Layer 1 before transitioning to Layer 3. The combined area (A1 + A2) remains nearly equal to the area (A) depicted in the preceding figure. Additionally, the electromagnetic fields of current loops A1 and A2 exhibit opposing directions, leading to partial cancellation of these fields. This cancellation helps mitigate electromagnetic interference.
For high-speed signals, blind vias are preferable to through-hole vias, as the latter can create transmission line stubs, causing reflections and delays. Blind vias reduce signal distortion and minimize impedance changes. As depicted in the figure below, a through-hole via traverses all six layers, resulting in the formation of an open-end transmission line without termination, leading to a 100% reflection. Additionally, the length of the stub introduces a delay. In the worst-case scenario, the original signal (blue) and its reflected counterpart (purple) on Layer 3 experience a phase shift of 180°, causing them to cancel each other out.
Transitioning the routing layer from Layer 1 (Top) to Layer 6 (Bottom), or from Layer 3 to Layer 6 (Bottom), requires careful consideration. This amplifies both the current loop area and electromagnetic field, potentially heightening electromagnetic interference levels. As illustrated in the figure below, the net initially follows a path on Layer 1 before transitioning to Layer 6. The combined current loop area (A3 + A4) significantly surpasses the area A shown in the preceding figure, although an opposite electromagnetic field direction. Consequently, the electromagnetic field strength and the potential for electromagnetic interference notably increase.
The simplest way to mitigate this issue is to relocate the via closer to either the source or the sink. As depicted in the figure below, the via is repositioned near the sink. This adjustment significantly reduces the combined current loop area (A5 + A6), thereby ensuring that the electromagnetic field remains at a lower level.
If relocating the via is not feasible, mitigating this issue can be achieved by adding a ground via around the signal via. This provides a return path for current, thereby maintaining electromagnetic field levels. As depicted in the figure below, the current loop area (A7 + A8) closely resembles area A in the previous figure. Additionally, the electromagnetic fields of current loops A7 and A8 exhibit opposing directions, leading to partial cancellation of these fields. This cancellation helps mitigate electromagnetic interference.
When routing signals on a 4-layer PCB, the arrangement of layers is vital for maintaining optimal signal integrity. The recommended layer stack-up is as follows:
Layer 1 (Top): Signal routing
Layer 2 (GND): Ground plane
Layer 3 (VCC): Power plane
Layer 4 (Bottom): Signal routing
Layers 1 and 4 are specifically designated for signal routing because they are adjacent to the ground and power planes, respectively. This adjacency allows for efficient paths for return currents, effectively reducing loop area and minimizing electromagnetic interference.
Referring to the figure below, the forward current flows along a net on Layer 1 (Top), while the return current flows back on the ground plane beneath the net.
As illustrated in the figure below, the forward current flows along a net on Layer 4 (Bottom). Meanwhile, the return current seeks the lowest impedance path for returning, which is on the power plane above the net. This return path is facilitated through bypass capacitors on the power pins of source and sink devices. Importantly, the area (A1) remains nearly equal to the area (A) depicted in the preceding figure, ensuring that the electromagnetic field remains at the same level.
Changing layers is typically unavoidable when routing on a 4-layer PCB. As depicted below, transitioning from Layer 1 to Layer 4 (or vice versa) occurs in the midst of source and sink devices. In such cases, without a bypass capacitor to facilitate high-frequency signal flows, the return current continues to flow through the ground plane. Consequently, the combined current loop area (A2 + A3) significantly increases compared to the area A shown in the preceding figure. This expansion results in heightened electromagnetic field strength and an increased potential for electromagnetic interference.
The simplest way to mitigate this issue is to relocate the via closer to either the source or the sink. As depicted in the figure below, the via is repositioned near the sink. This adjustment significantly reduces the combined current loop area (A4 + A5), thereby ensuring that the electromagnetic field remains at a lower level.
If relocating the via is not feasible, mitigating this issue can be achieved by incorporating a bypass capacitor near the transition point, where one end connects to the ground plane and the other end connects to the power plane. As depicted below, the return current flows through the bypass capacitor back to the ground plane. This arrangement ensures that the current loop area (A6 + A7) remains nearly identical to area A in the preceding figure, thereby maintaining a consistent electromagnetic field level.
Another solution involves adding a ground trace adjacent to the original net on Layer 4, providing a path for the return current. It's essential to terminate the ground trace with ground vias at both ends to ensure proper grounding and minimize impedance.
Referring to the schematic of a typical crystal oscillator below, it's crucial to minimize the area of the current loop A1, A2, and A3, as these loops typically carry significant current. Conversely, the resistance of Rf is relatively high, often in the range of several hundred kiloohms, resulting in minimal current flow through it. Consequently, any electromagnetic emission from this loop is negligible and can generally be disregarded.
The figure below illustrates the recommended placement and trace routing for a crystal oscillator. It's crucial to route the XI and XO nets as close as possible, with the remaining empty area filled with a ground copper to minimize loop area and mitigate electromagnetic interference.
Here are some other guidelines:
Grounding: Fully ground both the crystal and the clock traces in the oscillator circuit to establish a complete reference ground plane.
Compact Layout: Ensure a compact layout for the crystal oscillator circuit. Position capacitors between the crystal and the IC.
Avoiding High-Power Devices: Keep the crystal oscillator circuit away from high-power devices such as power chips, MOS transistors, inductors, and other components generating significant heat.
A 6-layer HDI PCB is recommended for SP7350 due to the stringent routing requirements of DDR3, DDR3L, DDR4, or LPDDR4 signal traces. The recommended stack-up for a 6-layer PCB is illustrated below:
Layer 1 (Top layer) and Layer 3 (L3_S layer): Dedicated to signal traces, both referencing Layer 2 (L2_GND), which serves as the ground plane.
Layer 6 (Bottom layer): Also designated for signal traces and refers to Layer 5 (L5_GND), another ground plane.
Layer 4 (L4_POWER): Acts as the power plane, with the system's power utilizing this plane in conjunction with the ground plane and bypass capacitors to achieve minimal impedance and ensure power integrity.
The following table provides reference widths and clearances for achieving target impedance between signal and ground planes:
For example:
For a single-end signal with 50 Ω impedance on Layer 1, set the trace width to 5 mils and clearance to 10 mils.
For a differential-pair signal with 90 Ω differential impedance on Layer 1, set the trace width to 4.5 mils and clearance to 6 mils.
Effective routing of power traces, planes, and the strategic placement of bypass capacitors are essential to establish a low-impedance path to ground. This is critical for minimizing voltage ripple, particularly under high-current conditions. Below is the table detailing the target impedance for each power domain to ensure optimal performance:
Power Pin | Maximum current (A) | Ripple Spec. | Target impedance (mΩ) |
VDD | 2.1 | 5% | 19.0 |
VDD_VV | 1.7 | 5% | 23.9 |
VDD_CA55 | 1.0 | 5% | 40.0 |
VDD_NPU | 5.4 | 5% | 7.4 |
These target impedance values are crucial for maintaining stable and reliable power delivery across different power domains, ensuring the system operates optimally.
Refer to the Power Distribution Network (PDN) simulation of the VDD_CA55 on the SP7350 Evaluation Board conducted using Ansys software.
The simulation results confirm that the impedance meets the criteria of being less than 40.0 mΩ, ensuring compliance with the design specifications.
Routing traces for DDR SDRAM requires careful planning and adherence to specific guidelines to maintain signal integrity and performance. Here are the general guidelines for routing traces for DDR SDRAM:
Length Matching:
Ensure that the lengths of data, address, and control signal traces are matched within tight tolerances to minimize skew and maintain synchronization.
Impedance Control:
Maintain consistent impedance along the traces to prevent signal reflections.
Use controlled impedance routing to match the characteristic impedance of the DDR signals.
Signal Integrity:
Avoid stubs and ensure a continuous signal path to minimize reflections.
Use ground vias to connect the signal layer to the ground plane for better signal return paths.
Routing Layers:
Utilize inner layers for routing DDR signals, especially for addressing and data bus to minimize interference and noise.
Power and Ground Planes:
Ensure a solid and continuous power and ground plane beneath DDR signal traces to provide a stable reference and reduce EMI.
Many thanks to Zoe for supplying the technical data presented below.
A LPDDR4 SDRAM chip has a bit width of 32, which means that only one chip is needed to establish a 32-bit width data bus. This streamlined configuration minimizes the complexity of routing signals from the physical layer (PHY) to the SDRAM chip.
It is recommended that DQ, DM and DQS signals of the same byte run on the same layer.
It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:
Power Pin | Maximum current (A) | Ripple Spec. | Target impedance (mΩ) |
DRAM_VDD | 0.415 | 2.0% | 38.6 |
DRAM_VDDQ | 0.705 | 2.5% | 39.0 |
BP_VAA | 0.00429 | 2.5% | 10479 |
Adhering to these target impedance values ensures optimal performance and reliability of the DDR PHY within the PCB design.
Refer to the Power Distribution Network (PDN) simulation of the DRAM_VDD on the SP7350 Evaluation Board conducted using Ansys software.
The simulation results confirm that the impedance meets the criteria of being less than 38.6 mΩ, ensuring compliance with the design specifications.
Refer to the Power Distribution Network (PDN) simulation of the DRAM_VDDQ on the SP7350 Evaluation Board conducted using Ansys software.
The simulation results confirm that the impedance meets the criteria of being less than 39.0 mΩ, ensuring compliance with the design specifications.
Skew limit: < 200 pS
Recommended skew: < 20 pS
Skew limit: DQS ±100 pS
Recommended skew: DQS ±10 pS
Recommended skew: CK ±10 pS
Skew limit can be relaxed if the timing budget and simulation results indicate that there is adequate margin.
Skew limit: -0.5 to +5.47 clock cycles
Recommended skew: CK ±60 pS
Maximum intra-pair skew: 3 pS
DQ: 50 Ω ±10%
DQS (diff.): 100 Ω ±10%
DM: 50 Ω ±10%
CS, CKE, ODT and CA: 50 Ω ±10%
CK (diff.): 100 Ω ±10%
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Eye height: 140 mV
Setup time: 67.1 pS (SDRAM contributions* and PHY contributions**)
Hold time: 69.8 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140 mV
Setup time: 73.8 pS (SDRAM contributions* and PHY contributions**)
Hold time: 76.2 pS (SDRAM contributions* and PHY contributions**)
Clock jitter: < 61.2 pS (SDRAM contributions* and PHY contributions**)
CS, ODT and CA (rectangular mask):
Eye height: 155 mV
Setup time: 159.7 pS (SDRAM contributions* and PHY contributions**)
Hold time: 159.7 pS (SDRAM contributions* and PHY contributions**)
*SDRAM contributions are obtained from JEDEC standard.
**PHY contributions include all those effects associated with PLL, macro blocks and I/O during transmitting and receiver operations. These effects include skews, pulse width distortion, jitter effects and training errors.
Vpk-pk (VDDQ): < 5% VDDQ
Vpk-pk (DRAM_VDD): < 4% VDD
Referring to reference layout of Layer 1 (Top) below, it is imperative to maintain a controlled impedance of 100 Ω for the four specified differential pairs, while single-end signals should adhere to a 50 Ω impedance standard. The sequence of the four differential pairs, from left to right, is as follows: (DRAM_SDQS1_T_A, DRAM_SDQS1_C_A), (DRAM_CK_C_A, DRAM_CK_T_A), (DRAM_CK_T_B, DRAM_CK_C_B), and (DRAM_SDQS1_T_B, DRAM_SDQS1_C_B).
Refer to reference layout of Layer 3 (L3_S) below, similarly, the impedance of the two specified differential pairs should be maintained at 100 Ω, while other single-end signals should adhere to a 50 Ω impedance standard. These two differential pairs, arranged from left to right, are: (DRAM_SDQS0_T_A, DRAM_SDQS0_C_A), and (DRAM_SDQS0_C_B, DRAM_SDQS0_T_B).
Referring to reference layout of Layer 6 (Bottom) below, the prescribed impedance for all single-end signals is 50 Ω, ensuring consistency and optimal signal integrity throughout the design. Note that bypass capacitors for PHY and SDRAM are all placed at this layer.
The maximum bit width of a DDR4 SDRAM chip is 16. Two DDR4 SDRAM chips are combined to create a 32-bit width data bus. Each DDR4 SDRAM chip has its own dedicated data bus: one handles DQ0 to DQ15, while the other manages DQ16 to DQ31. It is recommended that DQ, DM and DQS signals of the same byte run on the same layer. However, both chips share the control and address buses.
To route the control and address signals from the physical layer (PHY) to the two SDRAM chips, the T-topology methodology is recommended. This approach optimizes signal integrity and minimizes interference, ensuring reliable communication between the memory controller and the SDRAM chips.
It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:
Power Pin | Maximum current (A) | Ripple Spec. | Target impedance (mΩ) |
DRAM_VDD | 0.394 | 2.5% | 50.8 |
DRAM_VDDQ | 0.429 | 5.0% | 139.8 |
BP_VAA | 0.00429 | 2.5% | 10479 |
Adhering to these target impedance values ensures optimal performance and reliability of the DDR PHY within the PCB design.
Skew limit: < 200 pS
Recommended skew: < 20 pS
Skew limit: DQS ±100 pS
Recommended skew: DQS ±10 pS
Skew limit: 0 to 1UI*
Recommended skew: CK ±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85 pS
Maximum intra-pair skew: 3 pS
DQ: 50 Ω ±10%
DQS (diff.): 100 Ω ±10%
DM: 50 Ω ±10%
CS, CKE, ODT, command and address: 50 Ω ±10%
CK (diff.): 100 Ω ±10%
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Eye height: 120 mV
Setup time: 62.7 pS (SDRAM contributions* and PHY contributions**)
Hold time: 66 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140 mV
Setup time: 77.6 pS (SDRAM contributions* and PHY contributions**)
Hold time: 81 pS (SDRAM contributions* and PHY contributions**)
Clock jitter: < 39.8 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels:
510 mV (AC input logic low)
690 mV (AC input logic high)
Setup time: 176.8 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
535 mV (DC input logic low)
665 mV (DC input logic high)
Hold time: 180.8 pS (SDRAM contributions* and PHY contributions**)
*SDRAM contributions are obtained from JEDEC standard.
**PHY contributions include all those effects associated with PLL, macro blocks and I/O during transmitting and receiver operations. These effects include skews, pulse width distortion, jitter effects and training errors.
Vpk-pk (VDDQ): < 10% VDDQ
Vpk-pk (DRAM_VDD): < 5% VDD
The maximum bit width of a DDR3 SDRAM chip is 16. Typically, two DDR3 SDRAM chips are paired to form a 32-bit width data bus. Each chip manages a specific range of data lines: one handles DQ0 to DQ15, while the other manages DQ16 to DQ31. It is recommended that DQ, DM and DQS signals of the same byte run on the same layer. Despite this division, both chips share the control and address buses.
For routing of control and address signals from the physical layer (PHY) to the two SDRAM chips, the T-topology methodology is recommended. This strategy optimizes signal integrity and reduces interference, ensuring reliable communication between the memory controller and the SDRAM chips.
It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:
Power Pin | Maximum current (A) | Ripple Spec. | Target impedance (mΩ) |
DRAM_VDD | 0.344 | 2.5% | 58.2 |
DRAM_VDDQ | 0.638 | 5.0% | 117.6 |
BP_VAA | 0.00429 | 2.5% | 10479 |
Adhering to these target impedance values ensures optimal performance and reliability of the DDR PHY within the PCB design.
Skew limit: < 200 pS
Recommended skew: < 20 pS
Skew limit: DQS ±100 pS
Recommended skew: DQS ±10 pS
Skew limit: 0 to 1UI*
Recommended skew: CK ±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85 pS
Maximum intra-pair skew: 3 pS
DQ: 50 Ω ±10%
DQS (diff.): 100 Ω ±10%
DM: 50 Ω ±10%
CS, CKE, ODT, command and address: 50 Ω ±10%
CK (diff.): 100 Ω ±10%
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Setup levels:
615 mV (AC input logic low)
885 mV (AC input logic high)
Setup time: 136.5 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
650 mV (DC input logic low)
850 mV (DC input logic high)
Hold time: 124.3 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140 mV
Setup time: 123.5 pS (SDRAM contributions* and PHY contributions**)
Hold time: 166.5 pS (SDRAM contributions* and PHY contributions**)
Clock jitter: < 43 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels: 625 mV (AC input logic low)
875 mV (AC input logic high)
Setup time: 270.1 pS (SDRAM contributions* and PHY contributions**)
Hold levels: 650 mV (DC input logic low)
850 mV (DC input logic high)
Hold time: 217.2 pS (SDRAM contributions* and PHY contributions**)
*SDRAM contributions are obtained from JEDEC standard.
**PHY contributions include all those effects associated with PLL, macro blocks and I/O during transmitting and receiver operations. These effects include skews, pulse width distortion, jitter effects and training errors.
Vpk-pk (VDDQ): < 10% VDDQ
Vpk-pk (DRAM_VDD): < 5% VDD
The DDR3L SDRAM chip has a maximum bit width of 16. Typically, two DDR3L SDRAM chips are paired to form a 32-bit width data bus. Each chip manages its own dedicated data bus: one handles DQ0 to DQ15, while the other manages DQ16 to DQ31. It is recommended that DQ, DM and DQS signals of the same byte run on the same layer. Despite this division, both chips share the control and address buses.
For routing of control and address signals from the physical layer (PHY) to the two SDRAM chips, the T-topology methodology is recommended. This approach optimizes signal integrity and minimizes interference, ensuring reliable communication between the memory controller and the SDRAM chips.
It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:
Power Pin | Maximum current (A) | Ripple Spec. | Target impedance (mΩ) |
DRAM_VDD | 0.344 | 2.5% | 58.2 |
DRAM_VDDQ | 0.638 | 5.0% | 117.6 |
BP_VAA | 0.00429 | 2.5% | 10479 |
Adhering to these target impedance values ensures optimal performance and reliability of the DDR PHY within the PCB design.
Skew limit: < 200 pS
Recommended skew: < 20 pS
Skew limit: DQS ±100 pS
Recommended skew: DQS ±10 pS
Skew limit: 0 to 1UI*
Recommended skew: CK ±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85 pS
Maximum intra-pair skew: 3 pS
DQ: 50 Ω ±10%
DQS (diff.): 100 Ω ±10%
DM: 50 Ω ±10%
CS, CKE, ODT, command and address: 50 Ω ±10%
CK (diff.): 100 Ω ±10%
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Setup levels:
540 mV (AC input logic low)
810 mV (AC input logic high)
Setup time: 136.5 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
575 mV (DC input logic low)
775 mV (DC input logic high)
Hold time: 124.3 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140 mV
Setup time: 123.5 pS (SDRAM contributions* and PHY contributions**)
Hold time: 166.5 pS (SDRAM contributions* and PHY contributions**)
Clock jitter: < 43 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels:
550 mV (AC input logic low)
800 mV (AC input logic high)
Setup time: 270.1 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
575 mV (DC input logic low)
775 mV (DC input logic high)
Hold time: 217.2 pS (SDRAM contributions* and PHY contributions**)
*SDRAM contributions are obtained from JEDEC standard.
**PHY contributions include all those effects associated with PLL, macro blocks and I/O during transmitting and receiver operations. These effects include skews, pulse width distortion, jitter effects and training errors.
Vpk-pk (VDDQ): < 10% VDDQ
Vpk-pk (DRAM_VDD): < 5% VDD
Many thanks to Terry for providing the technical data presented below.
For optimal performance, it is recommended to position the SPI-NOR flash in close proximity to the SP7350, minimizing trace lengths as much as possible.
D[3:0] to CLK skew: ±150 mil
D[3:0], CSN, CLK: 50 Ω ±10%
For optimal performance, it is advised to position the SPI-NAND flash in close proximity to the SP7350, minimizing trace lengths as much as possible. Additionally, it's crucial to avoid routing traces near high-frequency digital signals to prevent interference.
D[3:0] to CLK skew: ±100 mil
D[3:0], CSN, CLK: 50 Ω ±10%
It is recommended that the NAND flash is as close as possible to the SP7350, and the traces should be as short as possible, and avoid close to high-frequency digital signals.
D[7:0] within the group: ±500 mils
WE# to D[7:0]: ±500 mils
CE, CLE, ALE to WE: ±500 mils
CE, CLE, ALE to RE#: ±500 mils
Trace Impedance: 50 Ω ±10%
To optimize performance, it is advisable to position the eMMC device in close proximity to the SP7350, minimizing trace lengths as much as possible. Additionally, it's crucial to avoid routing traces near high-frequency digital signals to prevent interference.
For single-ended signals, ensure that trace lengths run parallel to each other smoothly to maintain signal integrity. Avoid sharp corners, stubs, and crossovers in routing, as these can introduce impedance mismatches and signal reflections. Routing all single-ended signals on a single layer with effective ground shielding helps minimize noise and interference.
Skew of CLK, CMD, DQ and DS signals: ±50 mil
CLK, CMD, DQ and DS signals : 50 Ω ±10%
Referring to reference layout of Layer 1 (Top) below, all eMMC nets initially originate from SP7350 and traverse Layer 1. It is important to maintain a controlled impedance of 50 Ω for all eMMC nets whenever possible.
Referring to reference layout of Layer 3 (L3_S) below, CMD, D5, and DS nets are redirected to this layer to continue their path to the eMMC chip.
Layer 6 (Bottom) serves as the location for essential components like bypass capacitors and pull-up resistors. Placing these components at the bottom layer optimizes circuit functionality and net routing, ensuring overall system reliability.
Routing USB 2.0 signals requires careful consideration to maintain signal integrity and ensure reliable high-speed data transmission. Here are the general guidelines for routing USB 2.0 signals:
Within the pair, ensure the traces run smoothly in parallel and are matched in length. Avoid sharp corners, stubs, and crossovers in the routing.
Route all signal of differential pair on the single layer with well ground shielding. Any routing for differential pair signal with cross-plane and layer changing is not allowed.
Maximum intra-pair skew: 1 pS (~6mil)
DP/DM differential-pair: 90 Ω ±10%
In the reference layout below, the data differential pair of USB 2.0 is initially routed at Layer 3, and subsequently transition to Layer 6 towards a connector. It is crucial to maintain a controlled differential impedance of 90 Ω for this pair.
Routing USB 3.0 signals requires careful consideration to maintain signal integrity and ensure reliable high-speed data transmission. Here are the general guidelines for routing USB 3.0 signals:
Within the pair, the trace lengths should be run parallel smoothly to each other and matched in length. Make sure routing without any extremely cornering, stub, and crossover.
Provide a continuous and solid ground plane beneath the differential pairs to act as a reference plane and reduce EMI.
Conduct signal integrity testing and compliance testing to verify the performance and reliability of the USB 3.0 design.
Maximum intra-pair skew: 1 pS (~6mil)
Maximum intra-pair skew: 1 pS (~6mil)
TX or RX differential-pairs: 90 Ω ±10%
DP/DM differential-pair: 90 Ω ±10%
USB3_AVDD08: < 2.4 nH
USB3_DVDD08: < 2.4 nH
USB3_VDD33: < 2.8 nH
In the reference layout below, the six differential pairs of USB 3.0 are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. It is crucial to maintain a controlled differential impedance of 90 Ω for all pairs. From top to bottom, the differential pairs are: (USB30_TX1_DP_0, USB30_TX1_DM_0), (USB30_RX1_DP_0, USB30_RX1_DM_0), (USB30_TX0_DM_0, USB30_TX0_DP_0), (USB30_RX0_DM_0, USB30_RX0_DP_0), and (USB30_DM, USB30_DP).
It is recommended that the SD socket or SDIO device is as close as possible to the SP7350, and the traces should be as short as possible, and avoid close to high-frequency digital signals. For single-ended signals, ensure that trace lengths run parallel to each other smoothly. Avoid sharp corners, stubs, and crossovers in routing. Route all single-ended signals on a single layer with effective ground shielding.
D[3:0] and CMD to CLK skew: ±100 mils
CLK, CMD, D[3:0] signals : 50 Ω ±10%
In the reference layout below, the six nets of the SD card are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. Please maintain a controlled impedance of 50 Ω for all SD card signals throughout.
In the reference layout below, the six nets of the SDIO are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. Please maintain a controlled impedance of 50 Ω for all SDIO signals throughout.
Route the MIPI_AVSS traces alongside both sides of the differential pairs wherever possible. Within the pair, the trace lengths should be run parallel smoothly to each other. Make sure routing without any extremely cornering, stub, and cross over. Within the pair, the trace lengths should be run parallel to each other and matched in length. Route all signal of differential pair on the single layer with well ground shielding. Any routing for differential pair signal with cross-plane and layer changing is not allowed
Maximum intra-pair skew: 1 pS (~6mil)
Maximum intra-pair skew: 1 pS (~6mil)
Channel skew limit: clock ±66 pS
Data and clock differential-pairs: 100 Ω ±10%
In the reference layout below, the nets of the MIPI-RX2 are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPIRX2_DP2, MIPIRX2_DN2), (MIPIRX2_DN0, MIPIRX2_DP0), and (MIPIRX2_DP3, MIPIRX2_DN3).
From top to bottom, the differential pairs are: (MIPIRX2_CN, MIPIRX2_CP), and (MIPIRX2_DP1, MIPIRX2_DN1).
In the reference layout below, the nets of the MIPI-RX3 are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPIRX3_DP0, MIPIRX3_DN0), and (MIPIRX3_CN, MIPIRX3_CP).
The differential pair is: (MIPIRX3_DN1, MIPIRX3_DP1).
In the reference layout below, the three differential pairs of MIPI-RX4 are initially routed at Layer 1, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPI4_DP0, MIPI4_DN0), (MIPI4_SP, MIPI4_SN), and (MIPI4_DP1, MIPI4_DN1).
In the reference layout below, the five differential pairs of MIPI-RX5 are initially routed at Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPI5_DN2, MIPI5_DP2), (MIPI5_DN0, MIPI5_DP0), (MIPI5_SP, MIPI5_SN), (MIPI5_DN1, MIPI5_DP1), and (MIPI5_DP3, MIPI5_DN3).
In the reference layout below, the five differential pairs of MIPI-TX are initially routed at Layer 1, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPITX_DP3, MIPITX_DN3), (MIPITX_DP2, MIPITX_DN2), (MIPITX_SP, MIPITX_SN), (MIPITX_DP1, MIPITX_DN1), and (MIPITX_DP0, MIPITX_DN0).
For single-ended signals, ensure that trace lengths run parallel to each other smoothly to maintain signal integrity. Avoid sharp corners, stubs, and crossovers in routing, as these can introduce impedance mismatches and signal reflections.
Skew of TXD[3:0] and TXEN to TXC signals: ±100 mil
Skew of RXD[3:0] and RXDV to RXC signals: ±100 mil
TXD[3:0], TXEN, TXC, RXD[3:0], RXDV and RXC signals: 50 Ω ±10%
In the reference layout below, the nets of the RGMII are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. Please maintain a controlled impedance of 50 Ω for all RGMII signals throughout.
For single-ended signals, ensure that trace lengths run parallel to each other smoothly to maintain signal integrity. Avoid sharp corners, stubs in routing, as these can introduce impedance mismatches and signal reflections.
TXD[1:0], TXEN, REF_CLK, RXD[1:0] and CRS_DV signals : 50 Ω ±10%