Quad-core ARM® Cortex-A7(CA7) MPCore operating speed upto 960MHz
NEON multimedia processing engine with SIMDv2/VFPv4 ISA support
32KB L1 I-cache and 32KB L1 D-cache
512KB unified L2 cache
Generic Interrupt Controller (GIC) v2.0
Run as real time process unit
ARM926EJS operating speed up to 202 MHz
16KB L1 I-cache and 16KB L1 D-cache
Selectable 32KHz or 202MHz operating speed;
Intended to be used as a supervisory core;
Low-power operation—500uA @ 32KHz for the entire IC
All IO and peripherals are accessible by Cortex-A7/ARM926/8051
Dedicated pins for CA7 debug
Pin mux with other functions pin when production
Dedicated pins for debug
ARM926 and 8051 share the same JTAG debug port
Embedded DC-DC for computation unit, DDR3, and the core power
Only single 3.3V power supply[1]
3.3V to 0.90V for CA7
3.3V to 1.5V for DDR3
3.3V to 1.2V for Peripheral logics
Embedded temperature sensor (resolution 1°C) for temperature detection (temperature detection range from -40°C to 125°C)
[1] 1.2V external power is needed if 1.2V consumes current more than 1200mA
Embedded 128MB/512MB DDR3 1066 DRAM
SP7021-IS : built-in 128MB DDR3,
SP7021-IF : built-in 512MB DDR3
Support SPI NAND / SPI NOR / eMMC
Support BCH ECC
Support 1 bit/ 2bits/4-bits SPI_FLASH memory
RTC with leap year and daylight saving time correction by software
RTC with alarm timer with its own output port
CPU set the wakeup time, shutdown until this time
RTC wake up port to output pin and CPU interrupt
RTC connect to the backup power pin, charging battery without adding any charging circuit (??)
PWM:
Each module contain at least four synchronized PWM channels
output resolution region (ex. System clock is 202 Mhz ,pwm max 202Mhz/256 = 789KHz , Min 202/(256*65535) = 12 Hz)
Four General Purpose Timers:
Four 16 bit and up to two 32 bit timers/counters
Four Input Capture (IC) modules
Independent Watchdog Timers (WDT)
External boot image verified by ED25519 algorithm
External boot image will be signature-verified by internal ROM code and private/public key before loaded.
PKA Engine (RSA)
Hash Engine (SHA3, MD5)
Bulk Encryption/decryption Engine (AES)
Total 128 bytes
IC Vendor (before shipping)
Device ID, revision, 16 bits
The serial number
Two “registered” MAC addresses for two MAC controllers (each 48b)
User
64 bytes of one-time programmable memory for storing user IDs, hash data (for protection)
OTP is programmed by OTP program voltage pin. No extra programming circuit needed.
First port: eMMC 4.41 DDR 104MB/s for primary boot disk
Second port: SD card (SD 2.0) for removable media
Third port: SDIO (SD 2.0) interface for Wi-Fi module
Support boot from USB
Support USB video class (UVC).
Total 9 GPIO ports (GPIO0~GPIO8) and 8-bits for each port
Two ways of accessing individual GPIO lines:
Through 8-bit registers, where eight lines are read or written at the same time.
Bit-wise access: access single bit without disturbing other bits in the same register
Strong driving (16mA) for GPIO0 port
Separated interrupt configuration, 8 interrupt sources at GPIO1 port and need to be configured as wake-up source.
3.3V with 5V tolerance
Tri-state output pad with Schmitt trigger Input / enable / open collector / invert in or out for all ports
Two IEEE 802.3 10/100M ports with RMII interface
Support full and half duplex
Support Daisy Chain and NIC mode for different application scenarios
Support IEEE802.1Q VLAN tagging and un-tagging
Support MAC clone and MAC security
Support 4 traffic classes (compatible with IEEE802.1D-2004)
Support 1K MAC address table entries with programmable aging time
One console UART with only Tx/Rx lines
Four full function UARTs
128 bytes FIFO
Automatic RTS/CTS control
Clocking from 27MHz or external CLK input
Baud rates up to 921600 bps with Error rate under 3%
Independent Tx/Rx DMA functions for every UARTs.
Master mode and slave mode
SPI FIFO depth 8 bytes of RX and TX registers
Independent Tx/Rx DMA function for each port
I2C Master
I2C clock stretching and FIFO depth 32 bytes
Independent Tx/Rx DMA function for each port
Any signals of each function could map to any pin using pin mux mapping matrix
Pin mux is run time programmable
HDMI TX 1.4, resolution up to 720P
One MIPI CSI-RX port
Compliant with the MIPI CSI-2 Specification, rev 1.01 and MIPI D-PHY interface Specification, version 1.1
HS (high speed), LP (low power) modes supported
10Mbps per lane in LP mode
1.0Gbps per lane in HS mode
Support Power-down mode
Support MIPI CSI-2 short and long packet formats
Support MIPI CSI-2 4 data lane
Total bandwidth: 4 Gbps
Support MIPI CSI-2 data format: RAW8, RAW10, YUY2
Image Interface to core processor: Support 8 or 10 bits
Color depth / Bits per pixel: Support 8 or 10 bits per pixels
Support CCI or I2C master for Camera Control Interface
Camera pixel resolution: 1920x1080 (Including non-image data)https://sunplus-tibbo.atlassian.net/browse/FAQ-4
Support TTL interface panel for monitor, max resolution 1280x720.
Support TTL RGB888 output
I2S output up to 6 stereo channels (I2Sx3)
I2S input up to 4 stereo channels (I2Sx2)
1 SPDIF output
1 SPDIF input
Support TDM/PDM interface for 8 channel microphone array
PCM (TDM/I2S interface, 1-Rx+1-Tx interface)
TDM support 16/24/32bits, 8 channels, master/slave mode
FPGA platform expansion through the FBIO interface
FCC Class B for system level, Industrial temperature range -40°C ~ 85°C
20mmX20mm LQFP176-EP package