SP7350 Specification

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Table of Contents

1. Introduction

SP7350 (C3V) is a versatile chip engineered to provide robust computing power tailored for artificial intelligence applications, particularly those focused on vision processing. With its rich array of peripherals, it can operate effectively as a standalone product, such as in a sweeping robot. Additionally, it seamlessly integrates with other peripheral ICs (P-Chips) via Sunplus' unique Multi-Function Interface (MFI), enabling a diverse range of AI on Chip solutions.

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Standing as a sophisticated System-on-Chip (SOC), SP7350 features a versatile CPU and Neural Processing Unit (NPU) meticulously tailored for edge and AI computing tasks. With a formidable 4.5 TOPS AI processor and quad-core 1.8GHz ARM Cortex A55 CPU, SP7350 adeptly handles a wide range of edge AI and AIoT applications necessitating the processing of computer vision, video, image, audio, and more. Additionally, SP7350 integrates an ARM Cortex M4 Microcontroller Unit (MCU) to support machine control and peripheral Input/Output (IO). The MCU operates within an independent power domain, ensuring its functionality even when other function blocks are powered off.

SP7350 provides flexible interfacing and networking capabilities. USB3.1 DRD and USB2.0 OTG support both host and device functions, allowing SP7350 to serve as the central unit of a system or a dedicated processor within a device. Up to four MIPI CSI RX interfaces enable the connection of multiple cameras for applications like AMR/AGV or surveillance. An MIPI CSI/DSI TX interface empowers SP7350 to function as a camera controller or to output content to displays. For high-speed networking, SP7350 includes IEEE1588 GMAC, supporting 10/100/1000 Mbps Ethernet with an external PHY. Moreover, SP7350 features an on-chip H.264/JPEG codec, enabling efficient video/audio transmission suitable for consumer electronics or surveillance applications.

The MFI serves as a crucial component, facilitating high-speed data transmission between high- and low-processing chips via the CPU BUS. It can be programmed as a MIPI RX interface for MIPI cameras, with features such as automatic pin detection, signal switching, and error detection ensuring seamless and user-friendly connectivity.

Typical AI Processing tasks include motion-compensated processing, object detection, tracking, segmentation, face detection, and pose detection. SP7350 finds applications in various fields, including robotics, drones, AMR/AGV, surveillance, inspection, counting, people tracking, human interface for gaming/touch-less control, online meetings, and more.

Manufactured utilizing advanced 12nm chip technology, SP7350 offers the benefits of a small form factor and low power consumption, essential for constructing compact and energy-efficient devices.

2. Features

• CPU: Quad ARM Cortex-A55

  • 1.8 GHz (2.1 GHz for specific components)

  • Cache

    • L1 Cache: 32kB I-cache / 32kB D-cache

    • L2 Cache: 128kB

    • L3 Cache: 1MB

  • Support NEON advance SIMD architecture & Floating-point

  • Support DVFS

    • 0.5GHz ~1.8GHz for SP7350

    • 0.5GHz ~1.5GHz for SP7350L

  • Support individual core power down

  • Support 2/4 core configurable by e-fuse (OTP)

  • Support maximum frequency limited by e-fuse (OTP)

    • Maximum limited to 1.5GHz, 1.8GHz, and 2.1 GHz

  • Support Coresight debug solution

    • JTAG interface

    • CTI and PMU

    • ETB: 1k to 4k bytes buffer size per core

• NPU: AI and Parallel Processing Engine

  • Up to 4.1 TOPS (@900MHz) computing power

  • Support configurable operating frequency

  • Support individual controllable power domain.

  • Support OpenCL and OpenVX with Neural Network Extension

• MCU: ARM Cortex-M4

  • Support FPU

  • Support 400MHz, 200MHz, 100MHz and 25MHz

  • Support JTAG interface

• DDR SDRAM

  • LPDDR4-3200, DDR4-3200, LPDDR3/DDR3/DDR3L-1866

  • 2 channels, 16 bits per channel

  • Up to 8GB memory capacity

  • Support IO retention

• Internal SRAM

  • 256kB at main power domain

  • 384kB at CM4 (AO) power domain

    • For CM4 operation and DRAM IO retention data

• AXI DMA

  • Support 16 channels

  • Support memory-to-memory copy

  • Support hardware handshake for 8-bit NAND controller

• AHB DMA

  • Support 16 channels

  • Support memory-to-memory copy

  • Support hardware handshake for I2C and SPI controllers

• Boot Devices

  • eMMC device

    • Support both 1.8V and 3.3V IOVDD

    • Support SDR up to 200 MHz (only for IOVDD = 1.8V)

    • Support DDR up to 160 MHz (only for IOVDD = 1.8V)

  • SD card

    • Support SD 3.0

    • Support SDR up to 200MHz

  • SPI-NAND flash

    • Support SLC NAND only

    • Support up to 150Mz (only for 1.8V)

    • Support 1 or 2 planes 2k page-size dice

    • Support 1 plane 4k page-size dice

  • 8-bit NAND flash

    • Support 1.8V and 3.3V

    • Support 2k/4k/8 page-size dice

    • Support synchronous mode

  • SPI-NOR flash

    • Support 1/2/4-bit mode

    • Support 1.8V and 3.3V

    • Support up to 100Mz (only for 1.8V)

• In-system Programming for Flash Devices

  • eMMC, SPI-NAND, 8-bit NAND, and SPI-NOR

  • In-system programming through USB flash drives or SD cards

• Security

  • Support AES-128/192/256 encryption and decryption ECB, CBC, CTR mode

  • Support RSA

    • 256/512/1024/2048 bits encryption

    • modular exponentiation

  • Support HASH

    • SHA-2 256/512

    • SHA-3 224/256/384/512

    • MD5

  • GHASH for AES GCM mode

  • Support POLY 1305

  • Support Pseudo RNG

  • Support ARM TZC-400

  • Support secure boot

• SDIO

  • Support SD 3.0

  • Support transfer rate up to 104MB/s (UHS-1)

• Video and image codec

  • H.264/MVC, VP8 and JPEG encoding

  • H.264/SVC and JPEG decoding

  • Individual controllable power domain.

• USB3.1 (Gen. 1) Interface

  • Compliant to USB 3.1 Gen1 with DRD

  • Data rate up to 5Gbps

  • Integrated PHY

  • Support 4 sets of end-points (1 control and 3 data)

• USB2.0 Interface

  • Compliant to USB 2.0

  • Support OTG 1.0

  • Support High, Full and Low speeds

    • 4 in: 3 bulk/interrupt; 1 bulk/interrupt/isochronous

    • 4 out: bulk/interrupt; 1 bulk/interrupt/isochronous

• MIPI CSI RX

  • 1 MIPI-CSI2 RX 4D1C (1.5 Gbps per lane), support 4 virtual channel

  • 1 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel

  • 2 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel

    • Shared pins with CPIO (when CPIO disable, MIPI CSI RX enable)

    • 2 MIPI-CSI2 RX can be combined as 1 MIPI-CSI2 RX 4D1C, support 4 virtual channel

  • Max resolution: 2688x1944

• MIPI CSI/DSI TX

  • One MIPI TX output for either CSI or DSI

  • 4 lanes with 1.5Gbps per lane

  • DSI TX resolution up to 1920x1080

  • CSI TX resolution up to 3840x2880

• Audio Interfaces

  • One bidirectional I2S

  • Two unidirectional I2S

  • One 16-channel TDM

  • Configurable serial clock frequency

  • Support 16 bit audio format

  • Support both master and slave mode

  • Compliant with the IIS/PCM standard

• Ethernet Controller

  • Support 10/100/1000 Mbps data rate

  • Support RGMII and RMII interface (1.8V)

  • Support IEEE1588

• ADC

  • 12-bit SAR ADC with 4-channel

  • Sampling rate up to 1MHz

• PWM

  • Support 12 bits resolution

  • Support pre-scaling factor from 1 to 512

• Real-Time-Clock (RTC)

  • Independent Always-On power domain

  • 64 bits free-run timer with 32.768 kHz clock input

• SPI/I2C/UART

  • Up to seven UART interfaces

  • Up to six SPI interfaces (5 master, and 1 slave)

  • Up to ten I2C interfaces

• GPIO

  • Support total 106 GPIOs

  • Support software programmable driving strength for all GPIOs

  • Support 60 GPIOs with 1.8V/3.3V capability

    • 3 groups in AO-power domain

    • 2 groups in main-power domain

• Watchdog Timer

  • 32-bit counter

  • Up to 223 second

• Mailbox

  • For inter-processor communication between CA55 and CM4

• RTC

  • 32.768 kHz crystal

• Semaphore

  • Support read lock and write unlock

  • Support 16 channels

• Thermal Sensor

  • Placed at between CPU and NPU

  • Support two threshold temperatures (default disable)

    • Alarm threshold, interrupt to CPU

    • Shutdown threshold, for resetting all system

• Multi-Function Interface (MFI) and CPIO

  • Selectable proprietary CPIO and MIPI CSI-RX interfaces

  • CPIO interface

    • Supports 4 data lanes for both TX and RX, provides 1.0 GiB/s bandwidth

    • Support hardware auto calibration

    • Support hardware auto and/or software programmable SWAP and CROSSOVER modes

    • Support data swap

• Package: 15x15mm² FCCSP

3. Power Domains

The SP7350 architecture comprises six distinct power domains, each with its dedicated power supply that can be independently activated or deactivated. Illustrated in the figure below, these domains are: RTC, CM4 (AO), CA55, NPU, Video codec, and Main power domains.

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3.1 RTC Power Domain

The RTC power domain is typically powered by either a battery or a super capacitor. Its primary component is the real-time clock (RTC), which remains powered continuously to ensure uninterrupted operation. The RTC is driven by a 32.768 kHz crystal oscillator. Additionally, this domain includes circuitry for wake-up key detection. When the wake-up key is pressed for one second, activating the CM4_WAKEUP_KEY signal to HIGH, it triggers the enablement of power to the CM4 domain.

3.2 CM4 Power Domain

The CM4 power domain, also known as the Always On (AO) power domain, remains powered continuously, facilitating the operation of CM4 and its peripherals even when other domains like CA55 and the Main-power domain are powered down. Primarily, it manages the power flow for the CA55 and Main-power domains. CM4 possesses the capability to access all devices and peripherals within the Main-power domain even in the absence of power to the CA55.

In the current implementation, during normal operation, pressing the wake-up key for one second prompts CM4 to instruct Linux and CA55 to enter the suspend-to-RAM (STR) state. While in STR state, pressing the wake-up key for 0.3 seconds triggers CM4 to instruct CA55 to restore to normal operational status.

3.3 CA55 Power Domain

The CA55 power domain encompasses four Cortex A55 cores along with their L1, L2, and L3 caches. It supports Dynamic Voltage and Frequency Scaling (DVFS). The entire CA55 cluster can be powered down, and each core within CA55 can be individually deactivated. Given that CA55 is connected to the AXI bus in the Main-power domain, its operation necessitates the activation of the Main-power domain.

3.4 Main-power Domain

The Main-power domain hosts the majority of the devices and peripherals within the SP7350 system. All components within this domain are interconnected via three AXI buses. Notably, while the DDR SDRAM controller and PHY reside in the Main-power domain, the IO buffer of the PHY and DDR SDRAM chip are positioned in the CM4 power domain. This configuration ensures that the SDRAM remains in a retention state when the Main-power domain is powered off.

3.5 NPU Power Domain

The NPU's power can be individually toggled off when not in use. However, given its connection to the AXI bus in the Main-power domain, operating the NPU requires the Main-power domain to be activated.

3.6 Video-codec Power Domain

Similar to the NPU, the power supply to the video codec can be individually deactivated when not in use. Nevertheless, the video codec's operation necessitates the activation of the Main-power domain due to its connection to the AXI bus within that domain.

4. CPU, MCU, NPU and DRAM Interface

4.1 CPU

The CPU consists of a quad-core ARM Cortex-A55 architecture, featuring a floating-point unit (FPU) and NEON™ SIMD processing. Clock rates can reach up to 1.8GHz, with support for dynamic frequency scaling to optimize energy consumption. Cache memory comprises 32KB L1 I-cache, 32KB L1 D-cache, 128KB L2 cache, and 1MB L3 cache. TrustZone™ technology enhances security capabilities.

4.2 MCU

The MCU core is based on the ARM Cortex-M4 architecture, equipped with a floating-point unit. Operating at clock rates of 25MHz, 100MHz, 200MHz, and 400MHz, the MCU features an independent on-chip power domain. This allows the MCU to remain operational even when other chip power domains are shut off, enabling the implementation of deep-sleep mode. When CPUs return from deep sleep, DRAM must be configured in self-retention mode to maintain the previous state.

4.3 NPU

The NPU operates at clock rates of up to 900 MHz, delivering computing performance of up to 4.5 TOPS (Trillion Operations Per Second). Optimized for AI models based on convolutional neural networks, it includes a Parallel Processing Unit (PPU) with 32-bit floating-point pipelining and threading. For software development in parallel computing and video computing, both OpenCL and OpenVX are supported. The NPU resides in an independent power domain, allowing individual power-down control.

4.4 DRAM Interface

The supported types of DRAM include:

• LPDDR4 and DDR4, with speeds up to 3200 MT/s

• LPDDR3, DDR3L and DDR3, with speeds up to 1866 MT/s

The DRAM interface provides two channels with a 16-bit width for each channel. It supports up to 4GB DRAM chips, with a maximum total capacity of 8GB. To facilitate system suspending, the DRAM includes a self-refresh function for data retention when the chip core is powered down.

5. Boot Devices and In-System Programming

5.1 Boot Devices

The SP7350 (CPU) can be booted from various storage devices, including eMMC device, SD card, SPI-NAND, SPI-NOR, or 8-bit NAND flash.

5.2 In-System Programming (ISP)

System code can be programmed using either a USB flash drive connected to USB2 or USB3, or through an SD card.

6. USB Interfaces

6.1 USB 3.1 Gen 1 DRD

The USB3 interface is compliant to USB 3.1 Gen 1 standard with data rate of 5Gbps and supporting Dual-Role Device (DRD). USB 3.0 Dual-Role Data (USB3 DRD) enables a USB device to act as both a host and a peripheral device. This capability is also known as USB On-The-Go (USB OTG) in the context of USB 2.0.

With USB3 DRD, a device can dynamically switch between host and peripheral modes, allowing for more flexible and versatile usage scenarios. For example, a smartphone equipped with USB3 DRD can act as a USB host when connecting to USB peripherals like keyboards or flash drives, but can also function as a peripheral device when connected to a computer for data transfer.

When USB3 interface is operating in device mode, up to three endpoints can be configured as Interrupt, Bulk or Isochronous modes. These endpoints are also configurable as either input or output. The Control endpoint is fixed at endpoint number 0.

Note: All output endpoints share a buffer, while each input endpoint has its own input buffer.

6.2 USB 2.0 OTG

USB 2.0 supports both High-speed, Full-speed and Low-speed transfers and is compatible with both host and device configurations. USB On-The-Go (OTG) extends the capabilities of USB 2.0 by enabling devices to dynamically switch between host and peripheral roles as needed. Note that SP7350 only supports SRP and HNP, and does not supports ADP.

In device mode, USB 2.0 interfaces provide endpoint configuration options outlined in the table below. Besides the Control endpoint, users can configure up to four IN and four OUT endpoints for Bulk, Interrupt, or Isochronous data transfers. It's important to note:

• One of the endpoints 1, 2, 3, and 4 can be configured for Isochronous mode, while the others can be configured as Bulk or Interrupt mode.

• Similarly, one of the endpoints 5, 6, 7, and 8 can be configured for Isochronous mode, while the remaining endpoints can be configured for Bulk or Interrupt mode.

Here's the breakdown:

This breakdown illustrates the available options for configuring USB 2.0 endpoints.

7. Ethernet Controller

The Ethernet Media Access Controller (MAC) is a crucial component in networking systems, facilitating high-speed data transfer. It supports transfer rates of 10/100/1000 Mbps and interfaces with external transceivers (PHY) to establish Ethernet connectivity.

7.1 Register Configuration

The GMAC_PHYSEL (0xF88001DC[12]) register and CLKGEN_GMACPHY_SEL[1:0] (0xF88001DC [11:10]) register dictate the interface mode and corresponding TXC clock frequency. Proper configuration of the GMAC_PHYSEL and CLKGEN_GMACPHY_SEL registers is essential for ensuring optimal performance in each operating mode. Here's a breakdown of the configurations:

7.2 Pin Connections

The following table illustrates the pin connections for both RGMII (GMAC_PHYSEL = 0) and RMII (GMAC_PHYSEL = 1) interfaces. It's important to note that SP7350 only supports 1.8V PHY, regardless of the selected interface type.

Understanding and correctly implementing these configurations ensure seamless operation and optimal performance of the Ethernet MAC interface.

8. MIPI Interfaces and Display

8.1 MIPI CSI RX

The SP7350 boasts six MIPI CSI RX channels, although two are not accessible in this package configuration. The MIPI RX0, RX1, RX2, RX3, and RX4 channels support 2 data lanes (2D1C) each with 2 virtual channels. Additionally, the MIPI RX5 channel accommodates 4 data lanes (4D1C) with 4 virtual channels. It's noteworthy that MIPI RX2 can be adapted to support 4 data lanes (4D1C) with 4 virtual channels if MIPI RX3 remains unused. MIPI RX0 and RX1 are not accessible in this particular package variant.

Each data lane supports transmission speeds of up to 1.5 Gbps, offering a maximum resolution of 2688x1944. Refer to the table below for a comprehensive overview of all available channels.

It's important to note that RX2 and RX3 share pins with the CPIO interface. Therefore, only one of RX2/RX3 or the CPIO interface can be active at any given time.

8.2 MIPI CSI/DSI TX

One MIPI TX output port that can be configured as CSI for camera output or DSI for display output. This interface provides 4-lane with data rate of 1.5Gbps per lane.

8.2.1 MIPI DSI TX

• Support data format: RGB888, RGB666 with 18bit, RGB666 with 24bit, RGB565

• Maximum resolution: 1920x1080

8.2.2 MIPI CSI TX

• Support data format: YUY2, RGB888, RGB565, YUY2-10

• Maximum resolution: 3840x2880

• Image transfer from DRAM can support QoS

8.3 Display Engine

Display engine features:

• 4-Layer OSD

• Data format support: RGBA8888, RGB565, YUY2, 256 colors

• Maximum source resolution is 1920x1080

• 1 layer image, DRAM fetch format supports NV12, NV16 and YUV444.

• Support scaling up and down

• Maximum source resolution: 3840x2880

• Mixing Function

• Support 5 path mixing, Blending, Transparent, Opacity, Alpha Adjustment

• Support Gamma, 888 to 666 Dither, 888 to 565 Dither

9. Image and Video Codec

9.1 Video and JPEG Decoder

The decoder support real-time H.264/SVC and JPEG decoding.

H.264 decoding features:

• Maximum frame rate up to 60fps in 1080P resolution

• Video resolution from 48x48 to 1920x1920 with 16-pixel step size

• Baseline, main and high profiles

• Output color format: YCbCr420, YCbCr 400 (monochrome)

• Error detection and error concealment

JPEG decoding features:

• Maximum resolution 16368 x 16368 (256M pixels)

• Maximum pixel rate up to 76M pixels per second for real-time decoding

• Output JFIF color formats: YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4

• Error detection

Video post-processor features:

• Input format: YCbCr 420, YCbYCr422, YCrCb422, CbYCrY 422 and CrYCbY 422

• Output format: YCbCr420, YCbYCr422, YCrYCb422, CbYCrY422 and CrYCbY 422

• Input image size up to 16.7M pixels with max width of 8176 and max height of 8176. Step size is 16 pixels.

• Output image size up to 4096x4096 with step sizes of 8 pixels horizontally and 2 pixels vertically

• Image up and down scaling

• YCbCr to RGB conversion

• 2x2 ordered spatial dithering

• Alpha channel and alpha blending

• Image cropping and digital zoom for JPEG and video stand-alone mode

• Picture in picture

• Image 90/180/270 degrees rotation and horizontal/vertical flip

9.2 Video and JPEG Encoder

The encoder provides real-time H.264/MVC, VP8 and JPEG encoding.

H.264/MVC/VP8 encoding features:

• H.264 baseline, main and high profiles

• Input color format: YCbCr420, YCrCb420, YCbYCr 422, CbYCrY422

• Video size up to 1920x1920 with step size of 4 pixels

• Maximum frame rate: 1080P@30FPS for VP8 and 1080P@60FPS for H.264

• Bit rate from 10kbps to 40 Mbps for1080P@60FPS

JPEG encoding features:

• Support baseline

• Input color formats: YCbCr 420 and YCrCb420, YCbYCr422, CbYCrY422

• Maximum resolution 8176x8176 with step size of 4 pixels

• Maximum pixel rate up to 90M pixels per second for real-time processing

Pre-processor features:

• Color space conversion from YCbCr422 to YCbCr 420

• Maximum input resolution up to 8192x8192

• Image cropping

• Down-scaling

• Rotation by 90 or 270 degree

10. Audio Interface

The audio interface of our system comprises one bidirectional and two unidirectional I2S interfaces. Each interface supports 2-channel (L/R) operation and can function in either master or slave mode, with configurable clock frequency and LRCK polarity.

Within the chip, the I2S interfaces are situated in the Always-On power domain and are connected to the CM4 sub-system. They possess the capability to issue a wakeup signal to activate either the CM4 or CA55 processor cores.

10.1 Channel 0

Channel 0 is equipped with a bidirectional I2S interface, featuring the following signal specifications:

10.2 Channel 1

Channel 1 supports either input or output I2S interface, with the following signal specifications:

10.3 Channel 2

Channel 2 also supports either input or output I2S interface, with the following signal specifications:

10.4 Clock for external ADC or DAC

Two clock signals are provided for external audio ADC or DAC devices:

10.5 TDM

The TDM interface supports 6 channels for both input and output, with the following signal specifications:

10.6 SPDIF

A single-channel input or output is provided for debug use through the SPDIF interface:

11. Analog-Digital Converter

The SP7350 is equipped with a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), multiplexed across four channels. With a rapid sampling rate of up to 1MHz, this ADC delivers swift and efficient data acquisition capabilities. Its broad input range, from 0 to 1.8 volts (as powered by SAR12B_AVDD18), ensures seamless compatibility with an extensive array of input signals and diverse applications.

12. UART, SPI and I2C

The SP7350 offers a versatile array of interfacing functions, allowing users to configure up to 106 I/O ports for various purposes such as UART, SPI, I2C, SDIO, Ethernet PHY, audio, PWM, and more. In this section, we delve into the functionalities of UART, SPI, and I2C, highlighting their capabilities and configurations.

The UART, SPI, and I2C interfaces, with the exception of UADBG, reside within the Always-On power domain. This design ensures that even when the main power domain is inactive, these interfaces remain operational with the CM4 microcontroller.

12.1 UART

The SP7350 supports up to seven UART ports, boasting a maximum baud rate of 4 Mbps. Ports 1 and 2 feature hardware flow control for enhanced communication reliability. Additionally, the UADBG port is reserved for chip debugging purposes, featuring connectivity to the internal AXI bus through a specialized secure protocol.

12.2 SPI

SP7350 boasts up to five SPI ports, each designed to facilitate high-speed data transfer between interconnected devices. Among these, SPI 0, 1, 2, 3, and 4 operate as master controllers, while SPI 5 assumes the role of a slave controller. With a clock rate of up to 25MHz, these SPI ports offer rapid data transmission, catering to a diverse range of application requirements.

A meticulous examination of the SPI channels and their respective pin configurations provides invaluable insights into system connectivity. The following table elucidates the mode, signals, and pin assignments for each SPI channel:

12.3 I2C

SP7350 offers up to ten distinct ports, providing ample flexibility for system integration. These ports can function as either masters or slaves, facilitating bidirectional communication between interconnected devices. Moreover, the ports exhibit remarkable versatility, supporting Standard Mode (100 kHz), Fast Mode (400 kHz), and High-Speed Mode (1.2 MHz) for clock (SCL) frequencies.

The following table elucidates the pinout details for each I2C channel, delineating the signals, corresponding pins at Position X1 and Position X2.

13. RTC, STC, PWM and Clock Generators

13.1 Real-Time Clock

A 64-bit timer operates with a 32.768 kHz clock in an independent RTC power domain. Registers allow configuration of the timer within the range of 0 to 59 seconds, 0 to 59 minutes, 0 to 23 hours, and 0 to 65536 days. A maskable alarm interrupt can be set by configuring the second, minute, hour, and day.

13.2 System Time Counter (STC)

The SP7350 features seven System Time Counters (STCs), each comprising a 64-bit STC counter, a 24-bit RTC counter, a 32-bit watchdog counter, three 32-bit timers (timer 0, 1, 2), a 64-bit timer (timer 3), and a 34-bit ATC counter.

The STC counter operates as a 64-bit up-counting counter, with its trigger source scaled by a 15-bit pre-scaler (stc_prescaler). This pre-scaler can derive its source from either the system clock or an external clock, which can be a 25 MHz crystal or a 32.768 kHz crystal. Before reaching the pre-scaler, the external clock undergoes division by an 8-bit divider (ext_div).

The RTC counter functions as a 24-bit up-counting counter, triggered by the pre-scaler output of the STC and further divided by a 14-bit pre-scaler (rtc_prescaler). Meanwhile, the watchdog counter operates as a 32-bit down-counting counter, sharing the same trigger source as the STC counter. Upon reaching a count of 0, the watchdog counter can be configured to trigger various actions, including generating an interrupt, resetting the system, or executing a combination of interrupt followed by system reset.

The down-counting counters for timer 0, 1, and 2 have a width of 32 bits, whereas timer 3 boasts a wider 64-bit width. Their trigger sources can be configured to include the system clock, the pre-scaler output of the STC, the pre-scaler output of the RTC, or the output of another timer. Upon reaching a count of 0, the counters generate an interrupt, and the value stored in the reload register is automatically re-loaded into the counter in repeat mode.

Additionally, the ATC counter serves as a 24-bit up-counting counter, triggered by the pre-scaler output of the STC.

Here's a breakdown of the individual STCs, their power domain, group assignment, and interrupt target:

13.3 Pulse-Width Modulation (PWM)

Up to four 12-bit PWM channels are available with a pre-scaling factor from 1 to 512. The duty cycle is configurable from 0 to 100%, and the polarity of the output is also configurable.

13.4 Clock Generators

Various clocks can be generated by a digital PLL and output through GPIO pins, including CLKMCU, CLKWIFI, and CLKGNCMA. CLKRTC and CLKPHY output fixed frequencies of clocks. Note that digital PLL clocks offer average frequency, not stable frequencies. The source clock rate is 800 MHz, and the output clock rate is achieved by dividing the source clock rate by a divisor configured in registers. Clocks from the digital PLL may suffer from high jitter if the frequency of the generated clock is not divisible by the source frequency of the digital PLL.

14. GPIO

Up to 106 GPIOs are available, with 60 GPIO at 1.8V/3.3V voltage level and others at 1.8V voltage level. Driving strength is programmable.

14.1 Group of GPIO

The GPIO pins of SP7350 are organized into 10 distinct groups, each with its dedicated power supply. Refer to the table below for a breakdown of the power domains, supplying voltages, hardware pin names, and the corresponding supplying power pins for all IO pins of SP7350:

This table delineates the power domains and their respective supplying voltages, along with the hardware pin names and their corresponding supplying power pins for all IO pins of SP7350. Such organization facilitates efficient management and utilization of GPIO pins within the system.

14.2 Table of Default State of Power-on of GPIO

• ST (Schmitt Trigger Input): 1 indicates enabled, 0 indicates disabled.

• DS[3:0] (Driving Strength): Refer to Table 15.4.1 for values.

• SL (Slew Rate Control): 1 indicates enabled, 0 indicates disabled.

• PE (Pull Enable): 1 indicates pull-up/down enabled, 0 indicates disabled.

• PS (Pull Selector): 1 indicates pull-up, 0 indicates pull-down.

• SPU (Strong Pull Up): 1 indicates enabled, 0 indicates disabled.

14.3 Table of Default State of Power-on of DVIO

• ST (Schmitt Trigger Input): 1 indicates enabled, 0 indicates disabled.

• DS[3:0] (Driving Strength): Refer to Table 15.4.2 for values.

• PU (Pull Up): 1 indicates pull-up, 0 indicates disabled.

• PD (Pull Down): 1 indicates pull-down, 0 indicates disabled.

14.4 GPIO Interrupt

The SP7350 provides eight external interrupt inputs from configured GPIO pins. The table below lists the external interrupts 0 to 7 and the corresponding pins each interrupt can be configured with:

In the table, X1 denotes the 1^st signal output position. X2 denotes the 2^nd signal output position. X3 denotes the 3^rd signal output position. X11 denotes the 11^th signal output position.

14.5 Alternative Function of GPIO

Many GPIO (General Purpose Input/Output) pins offer alternative functions, providing versatility in their usage. These alternatives may consist of one, two, or more sets of output pins. For instance, I2C0 can be configured to output signals either at AO_MX4 (I2C0_CLK) and AO_MX5 (I2C0_DATA), or at AO_MX18 (I2C0_CLK) and AO_MX19 (I2C0_DATA). Below is a comprehensive table listing the alternatives for all GPIO pins: