C3V Specification

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Table of Contents

1. Introduction

SP7350 (C3V) is a versatile chip engineered to provide robust computing power tailored for artificial intelligence applications, particularly those focused on vision processing. With its rich array of peripherals, it can operate effectively as a standalone product, such as in a sweeping robot. Additionally, it seamlessly integrates with other peripheral ICs (P-Chips) via Sunplus' unique Multi-Function Interface (MFI), enabling a diverse range of AI on Chip solutions.

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Standing as a sophisticated System-on-Chip (SOC), SP7350 features a versatile CPU and Neural Processing Unit (NPU) meticulously tailored for edge and AI computing tasks. With a formidable 4.6 TOPS AI processor and quad-core 2.1 GHz ARM Cortex A55 CPU, SP7350 adeptly handles a wide range of edge AI and AIoT applications necessitating the processing of computer vision, video, image, audio, and more. Additionally, SP7350 integrates an ARM Cortex M4 Microcontroller Unit (MCU) to support machine control and peripheral Input/Output (IO). The MCU operates within an independent power domain, ensuring its functionality even when other function blocks are powered off.

SP7350 provides flexible interfacing and networking capabilities. USB3.1 DRD and USB2.0 OTG support both host and device functions, allowing SP7350 to serve as the central unit of a system or a dedicated processor within a device. Up to four MIPI CSI RX interfaces enable the connection of multiple cameras for applications like AMR/AGV or surveillance. An MIPI CSI/DSI TX interface empowers SP7350 to function as a camera controller or to output content to displays.

The SP7352 integrates a high-performance Image Signal Processor (ISP) capable of handling resolutions up to 5 megapixels (2688×1944). The ISP supports dual-channel input for 10-bit or 12-bit Bayer data with HDR capability, or a single channel for 10-bit or 12-bit RGBIR input. It delivers flexible output options in YUV 4:2:0, 4:2:2, and 4:4:4 formats, available in both semi-planar and planar configurations.

For high-speed networking, SP7350 includes IEEE1588 GMAC, supporting 10/100/1000 Mbps Ethernet with an external PHY. Moreover, SP7350 features an on-chip H.264/JPEG codec, enabling efficient video/audio transmission suitable for consumer electronics or surveillance applications.

The MFI serves as a crucial component, facilitating high-speed data transmission between high- and low-processing chips via the CPU BUS. It can be programmed as a MIPI RX interface for MIPI cameras, with features such as automatic pin detection, signal switching, and error detection ensuring seamless and user-friendly connectivity.

Typical AI Processing tasks include motion-compensated processing, object detection, tracking, segmentation, face detection, and pose detection. SP7350 finds applications in various fields, including robotics, drones, AMR/AGV, surveillance, inspection, counting, people tracking, human interface for gaming/touch-less control, online meetings, and more.

Manufactured utilizing advanced 12nm chip technology, SP7350 offers the benefits of a small form factor and low power consumption, essential for constructing compact and energy-efficient devices.

2. Features

• CPU: Quad ARM Cortex-A55

  • 1.8 GHz (2.1 GHz for specific components)

  • Cache

    • L1 Cache: 32kB I-cache / 32kB D-cache

    • L2 Cache: 128kB

    • L3 Cache: 1MB

  • Support NEON advance SIMD architecture & Floating-point

  • Support DVFS

    • 0.5GHz ~1.8GHz for SP7350

    • 0.5GHz ~1.5GHz for SP7350L

  • Support individual core power down

  • Support 2/4 core configurable by e-fuse (OTP)

  • Support maximum frequency limited by e-fuse (OTP)

    • Maximum limited to 1.5GHz, 1.8GHz, and 2.1 GHz

  • Support Coresight debug solution

    • JTAG and SWD interface

    • CTI and PMU

    • ETB: 1k to 4k bytes buffer size per core

• NPU: AI and Parallel Processing Engine

  • 4.1 TOPS (@900MHz) computing power

  • Up to 4.6 TOPS (@1GHz) for specific components

  • Support configurable operating frequency

  • Support individual controllable power domain.

  • Support OpenCL and OpenVX with Neural Network Extension

• ISP (only for SP7502)

  • Support for images sizes: 5 mega pixels (2688x1944) ~ VGA (640x480)

  • Support for input formats: Bayer and RGBIR raw

  • Support for output formats: Planar / Semi-planar YUV444, YUV422, YUV420

  • Support for HDR, AE, AWB, DPC,LSC, 3DNR, WDR Demosaic, CCM, Gamma, RGB2TUV, LCE, CRN, Y_Curve, EE, 3DNR, Scalar

• MCU: ARM Cortex-M4

  • Support FPU

  • Support 400MHz, 200MHz, 100MHz and 25MHz

  • Support JTAG interface

• DDR SDRAM

  • LPDDR4-3200, DDR4-2666, DDR3/DDR3L-1866

  • 2 channels, 16 bits per channel

  • Up to 8GB memory capacity

  • Support IO retention

• Internal SRAM

  • 256kB at main power domain

  • 384kB at CM4 (AO) power domain

    • For CM4 operation and DRAM IO retention data

• AXI DMA

  • Support 16 channels

  • Support memory-to-memory copy

  • Support hardware handshake for 8-bit NAND controller

• AHB DMA

  • Support 16 channels

  • Support memory-to-memory copy

  • Support hardware handshake for I2C and SPI controllers

• Boot Devices

  • eMMC device

    • Support both 1.8V and 3.3V IOVDD

    • Support SDR up to 200 MHz (only for IOVDD = 1.8V)

    • Support DDR up to 160 MHz (only for IOVDD = 1.8V)

  • SD card

    • Support SD 3.0

    • Support SDR up to 200MHz

  • SPI-NAND flash

    • Support SLC NAND only

    • Support up to 150Mz (only for 1.8V)

    • Support 1 or 2 planes 2k page-size dice

    • Support 1 plane 4k page-size dice

  • 8-bit NAND flash

    • Support 1.8V and 3.3V

    • Support 2k/4k/8 page-size dice

    • Support synchronous mode

  • SPI-NOR flash

    • Support 1/2/4-bit mode

    • Support 1.8V and 3.3V

    • Support up to 100Mz (only for 1.8V)

• In-system Programming for Flash Devices

  • eMMC, SPI-NAND, 8-bit NAND, and SPI-NOR

  • In-system programming through USB flash drives or SD cards

• Security

  • Support AES-128/192/256 encryption and decryption ECB, CBC, CTR mode

  • Support RSA

    • 256/512/1024/2048 bits encryption

    • modular exponentiation

  • Support HASH

    • SHA-2 256/512

    • SHA-3 224/256/384/512

    • MD5

  • GHASH for AES GCM mode

  • Support POLY 1305

  • Support Pseudo RNG

  • Support ARM TZC-400

  • Support secure boot

• SDIO

  • Support SD 3.0

  • Support transfer rate up to 104MB/s (UHS-1)

• Video and image codec

  • H.264/MVC, VP8 and JPEG encoding

  • H.264/SVC and JPEG decoding

  • Individual controllable power domain.

• USB3.1 (Gen. 1) Interface

  • Compliant to USB 3.1 Gen1 with DRD

  • Data rate up to 5Gbps

  • Integrated PHY

  • Support 4 sets of end-points (1 control and 3 data)

• USB2.0 Interface

  • Compliant to USB 2.0

  • Support OTG 1.0

  • Support High, Full and Low speeds

    • 4 in: 3 bulk/interrupt; 1 bulk/interrupt/isochronous

    • 4 out: bulk/interrupt; 1 bulk/interrupt/isochronous

• MIPI CSI RX

  • 1 MIPI-CSI2 RX 4D1C (1.5 Gbps per lane), support 4 virtual channel

  • 1 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel

  • 2 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel

    • 2 MIPI-CSI2 RX can be combined as 1 MIPI-CSI2 RX 4D1C, support 4 virtual channel

  • Max resolution: 2688x1944

• MIPI CSI/DSI TX

  • One MIPI TX output for either CSI or DSI

  • 4 lanes with 1.5Gbps per lane

  • DSI TX resolution up to 1920x1080

  • CSI TX resolution up to 3840x2880

• Audio Interfaces

  • One bidirectional I2S

  • Two unidirectional I2S

  • One 16-channel TDM

  • Configurable serial clock frequency

  • Support 16 bit audio format

  • Support both master and slave mode

  • Compliant with the IIS/PCM standard

• Ethernet Controller

  • Support 10/100/1000 Mbps data rate

  • Support RGMII and RMII interface (1.8V)

  • Support IEEE1588

• ADC

  • 12-bit SAR ADC with 4-channel

  • Sampling rate up to 1MHz

• PWM

  • Support 12 bits resolution

  • Support pre-scaling factor from 1 to 512

• Real-Time-Clock (RTC)

  • Independent Always-On power domain

  • 64 bits free-run timer with 32.768 kHz clock input

• SPI/I2C/UART

  • Up to seven UART interfaces

  • Up to six SPI interfaces (5 master, and 1 slave)

  • Up to ten I2C interfaces

• GPIO

  • Support total 106 GPIOs

  • Support software programmable driving strength for all GPIOs

  • Support 60 GPIOs with 1.8V/3.3V capability

    • 3 groups in AO-power domain

    • 2 groups in main-power domain

• Watchdog Timer

  • 32-bit counter

  • Up to 223 second

• Mailbox

  • For inter-processor communication between CA55 and CM4

• RTC

  • 32.768 kHz crystal

• Semaphore

  • Support read lock and write unlock

  • Support 16 channels

• Thermal Sensor

  • Placed at between CPU and NPU

  • Support two threshold temperatures (default disable)

    • Alarm threshold, interrupt to CPU

    • Shutdown threshold, for resetting all system

• Package: 15x15mm² FCCSP

3. Power Domains

The SP7350 architecture comprises six distinct power domains, each with its dedicated power supply that can be independently activated or deactivated. Illustrated in the figure below, these domains are: RTC, CM4 (AO), CA55, NPU, Video codec, and Main power domains.

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3.1 RTC Power Domain

The RTC power domain is typically powered by either a battery or a super capacitor. Its primary component is the real-time clock (RTC), which remains powered continuously to ensure uninterrupted operation. The RTC is driven by a 32.768 kHz crystal oscillator.

In addition to the clock function, this domain includes circuitry for wake-up key detection. When the wake-up key is pressed for one second, the CM4_WAKEUP_KEY signal goes HIGH. This triggers internal logic that automatically sets the CM4_PWR_EN pin to HIGH, enabling power to the CM4 power domain.

Conversely, if the wake-up key is held for more than 10 seconds, the CM4_PWR_EN pin is forcibly set to LOW by the same internal logic, shutting down power to the CM4 domain.

3.2 CM4 Power Domain

The CM4 power domain, also known as the Always On (AO) power domain, remains powered continuously, facilitating the operation of CM4 and its peripherals even when other domains like CA55 and the Main-power domain are powered down. Primarily, it manages the power flow for the CA55 and Main-power domains. CM4 possesses the capability to access all devices and peripherals within the Main-power domain even in the absence of power to the CA55.

In the current implementation, during normal operation, pressing the wake-up key for one second prompts CM4 to instruct Linux and CA55 to enter the suspend-to-RAM (STR) state. While in STR state, pressing the wake-up key for 0.3 seconds triggers CM4 to instruct CA55 to restore to normal operational status.

3.3 CA55 Power Domain

The CA55 power domain encompasses four Cortex A55 cores along with their L1, L2, and L3 caches. It supports Dynamic Voltage and Frequency Scaling (DVFS). The entire CA55 cluster can be powered down, and each core within CA55 can be individually deactivated. Given that CA55 is connected to the AXI bus in the Main-power domain, its operation necessitates the activation of the Main-power domain.

3.4 Main-power Domain

The Main-power domain hosts the majority of the devices and peripherals within the SP7350 system. All components within this domain are interconnected via three AXI buses. Notably, while the DDR SDRAM controller and PHY reside in the Main-power domain, the IO buffer of the PHY and DDR SDRAM chip are positioned in the CM4 power domain. This configuration ensures that the SDRAM remains in a retention state when the Main-power domain is powered off.

3.5 NPU Power Domain

The NPU's power can be individually toggled off when not in use. However, given its connection to the AXI bus in the Main-power domain, operating the NPU requires the Main-power domain to be activated.

3.6 Video-codec Power Domain

Similar to the NPU, the power supply to the video codec can be individually deactivated when not in use. Nevertheless, the video codec's operation necessitates the activation of the Main-power domain due to its connection to the AXI bus within that domain.

4. CPU, NPU, MCU and DRAM Interface

4.1 CPU

The CPU consists of a quad-core ARM Cortex-A55 architecture, featuring a floating-point unit (FPU) and NEON™ SIMD processing. It operates at clock rates of up to 1.8 GHz, with support for dynamic frequency scaling to optimize energy efficiency. For specific components, clock speeds can reach up to 2.1 GHz. The CPU features a hierarchical cache structure, including a 32 KB L1 instruction cache, a 32 KB L1 data cache, a 128 KB L2 cache, and a 1 MB L3 cache. Additionally, TrustZone™ technology bolsters its security capabilities.

4.2 NPU

The NPU operates at clock rates of 900 MHz, achieving a computing performance of 4.1 TOPS (Trillion Operations Per Second). For certain components, the clock rate increases to 1 GHz, delivering up to 4.6 TOPS. Optimized for AI models based on convolutional neural networks, it includes a Parallel Processing Unit (PPU) with 32-bit floating-point pipelining and threading. For software development in parallel computing and video computing, both OpenCL and OpenVX are supported. The NPU resides in an independent power domain, allowing individual power-down control.

4.3 MCU

The MCU core is based on the ARM Cortex-M4 architecture, equipped with a floating-point unit. Operating at clock rates of 25MHz, 100MHz, 200MHz, and 400MHz, the MCU features an independent on-chip power domain. This allows the MCU to remain operational even when other chip power domains are shut off, enabling the implementation of deep-sleep mode. When CPUs return from deep sleep, DRAM must be configured in self-retention mode to maintain the previous state.

4.4 DRAM Interface

The supported types of DRAM include:

• LPDDR4, with speeds up to 3200 MT/s

• DDR4, with speeds up to 2666 MT/s

• DDR3 and DDR3L, with speeds up to 1866 MT/s

The DRAM interface provides two channels with a 16-bit width for each channel. It supports up to 4GB DRAM chips, with a maximum total capacity of 8GB. To facilitate system suspending, the DRAM includes a self-refresh function for data retention when the chip core is powered down.

5. Boot Devices and In-System Programming

5.1 Boot Devices

The SP7350 (CPU) can be booted from various storage devices, including eMMC device, SD card, SPI-NAND, SPI-NOR, or 8-bit NAND flash.

5.2 In-System Programming (ISP)

System code can be programmed using either a USB flash drive connected to USB2 or USB3, or through an SD card.

6. USB Interfaces

6.1 USB 3.1 Gen 1 DRD

The USB3 interface is compliant to USB 3.1 Gen 1 standard with data rate of 5Gbps and supporting Dual-Role Device (DRD). USB 3.0 Dual-Role Data (USB3 DRD) enables a USB device to act as both a host and a peripheral device. This capability is also known as USB On-The-Go (USB OTG) in the context of USB 2.0.

With USB3 DRD, a device can dynamically switch between host and peripheral modes, allowing for more flexible and versatile usage scenarios. For example, a smartphone equipped with USB3 DRD can act as a USB host when connecting to USB peripherals like keyboards or flash drives, but can also function as a peripheral device when connected to a computer for data transfer.

When USB3 interface is operating in device mode, up to three endpoints can be configured as Interrupt, Bulk or Isochronous modes. These endpoints are also configurable as either input or output. The Control endpoint is fixed at endpoint number 0.

Note: All output endpoints share a buffer, while each input endpoint has its own input buffer.

6.2 USB 2.0 OTG

USB 2.0 supports both High-speed, Full-speed and Low-speed transfers and is compatible with both host and device configurations. USB On-The-Go (OTG) extends the capabilities of USB 2.0 by enabling devices to dynamically switch between host and peripheral roles as needed. Note that SP7350 only supports SRP and HNP, and does not supports ADP.

In device mode, USB 2.0 interfaces provide endpoint configuration options outlined in the table below. Besides the Control endpoint, users can configure up to four IN and four OUT endpoints for Bulk, Interrupt, or Isochronous data transfers. It's important to note:

• One of the endpoints 1, 2, 3, and 4 can be configured for Isochronous mode, while the others can be configured as Bulk or Interrupt mode.

• Similarly, one of the endpoints 5, 6, 7, and 8 can be configured for Isochronous mode, while the remaining endpoints can be configured for Bulk or Interrupt mode.

Here's the breakdown:

This breakdown illustrates the available options for configuring USB 2.0 endpoints.

7. Ethernet Controller

The Ethernet Media Access Controller (MAC) is a crucial component in networking systems, facilitating high-speed data transfer. It supports transfer rates of 10/100/1000 Mbps and interfaces with external transceivers (PHY) to establish Ethernet connectivity.

7.1 Register Configuration

The GMAC_PHYSEL (0xF88001DC[12]) register and CLKGEN_GMACPHY_SEL[1:0] (0xF88001DC [11:10]) register dictate the interface mode and corresponding TXC clock frequency. Proper configuration of the GMAC_PHYSEL and CLKGEN_GMACPHY_SEL registers is essential for ensuring optimal performance in each operating mode. Here's a breakdown of the configurations:

7.2 Pin Connections

The following table illustrates the pin connections for both RGMII (GMAC_PHYSEL = 0) and RMII (GMAC_PHYSEL = 1) interfaces. It's important to note that SP7350 only supports 1.8V PHY, regardless of the selected interface type.

Understanding and correctly implementing these configurations ensure seamless operation and optimal performance of the Ethernet MAC interface.

8. MIPI Interfaces and Display

8.1 MIPI CSI RX

The SP7350 boasts six MIPI CSI RX channels, although two are not accessible in this package configuration. The MIPI RX0, RX1, RX2, RX3, and RX4 channels support 2 data lanes (2D1C) each with 2 virtual channels. Additionally, the MIPI RX5 channel accommodates 4 data lanes (4D1C) with 4 virtual channels. It's noteworthy that MIPI RX2 can be adapted to support 4 data lanes (4D1C) with 4 virtual channels if MIPI RX3 remains unused. MIPI RX0 and RX1 are not accessible in this particular package variant.

Each data lane supports transmission speeds of up to 1.5 Gbps, offering a maximum resolution of 2688x1944. Refer to the table below for a comprehensive overview of all available channels.

8.2 MIPI CSI/DSI TX

One MIPI TX output port that can be configured as CSI for camera output or DSI for display output. This interface provides 4-lane with data rate of 1.5Gbps per lane.

8.2.1 MIPI DSI TX

• Support data format: RGB888, RGB666 with 18bit, RGB666 with 24bit, RGB565

• Maximum resolution: 1920x1080

8.2.2 MIPI CSI TX

• Support data format: YUY2, RGB888, RGB565, YUY2-10

• Maximum resolution: 3840x2880

• Image transfer from DRAM can support QoS

8.3 Display Engine

Display engine features:

• 4-Layer OSD

• Data format support: RGBA8888, RGB565, YUY2, 256 colors

• Maximum source resolution is 1920x1080

• 1 layer image, DRAM fetch format supports NV12, NV16 and YUV444.

• Support scaling up and down

• Maximum source resolution: 3840x2880

• Mixing Function

• Support 5 path mixing, Blending, Transparent, Opacity, Alpha Adjustment

• Support Gamma, 888 to 666 Dither, 888 to 565 Dither

9. Image Signal Processor (Only for SP7352)

An Image Signal Processor (ISP) is a specialized digital signal processor that takes the raw, unprocessed data directly from an image sensor and transforms it into a high-quality digital image for human viewing or further processing. The image sensor initially captures light passing through a lens, converting it into a raw digital signal. The ISP then reconstructs a full-color image by processing the primary color components (red, green, and blue).

9.1 ISP Features

The ISP feature includes:

• Supports resolutions up to 5 megapixels (2688x1944)

• Support for input formats: Bayer and RGBIR raw

• Support for output formats: Planar / Semi-planar YUV444, YUV422, YUV420

• Automatic Exposure (AE)

• Automatic White Balance (AWB)

• Color Gain and Black Level Calibration

• High Dynamic Range (HDR)

• Lens Shading Correction (LSC)

• Defect Pixel Correction (DPC)

• Bayer Noise Reduction (BNR, 2D NR)

• Wide Dynamic Range (WDR)

• Color Interpolation (De-mosaic)

• Color Correct Matrix (CCM)

• Gamma Correction (or Y Curve)

• Color Space Transform (CST)

• Local Contrast Enhancement (LCE)

• Chroma Noise Reduction (CNR)

• Edge Enhancement (EE)

• Temporal Noise Reduction (3D NR)

• Scaler