The aim of this document is to explain how to setup pins of SP7350 in device-tree source. SP7350 has 106 general purpose IO (GPIO) pins which are multiplexed with other special functions, like eMMC device, SPI-NOR flash, SPI-NAND flash, Ethernet PHY (RGMII or RMII interface), UART, I2C pins, and etc.

The following sections will explain how to setup GPIOs and special function pins in device-tree source file. Note that the same device-tree source file is used by U-Boot and Linux in SP7350. Both Pinctrl drivers support generic helper bindings.

Table of Contents

IO Pins

In the Linux, name of IO pin is in form of GPIO(id), like GPIO0, GPIO1, GPIO2, …, GPIO105, and etc. These IO pins of SP7350 are categorized, based on their operating voltage, into two groups:

• Single-supply IO pins: The IO pins operate on a single power supply, specifically at 1.8V.

• Dual-supply IO pins: The IO pins offer a dual power supply option, supporting both 1.8V and 3.0V. These pins are referred to as DVIO pins in the subsequent sections.

Refer to table below for a breakdown of power domain, supplying voltage, pin name (hardware pin name), supplying power pins of all IO pins of SP7350:

Voltage Mode Select

Beyond configuring the 1.8V or 3.0V power to supply pins of a DVIO group in circuit boards (hardware), setting up the voltage mode select (ms control) control-bits is crucial for the normal operation of IO pins. The following properties configure voltage mode select control-bits in the Device Tree Source (DTS) file:

These properties should be set in the pinctrl node in the DTS file. For example:

Default voltage is “3V0”.

Pin Multiplexing Nodes

• function - the multiplex function to select.

• groups - the list of groups to select with this function. Either this or "pins" must be specified.

• pins - the list of pins to select with this function. Either this or "groups" must be specified.

Refer to examples below:

Set a Single Pin to GPIO function

Set pin GPIO0 to GPIO function.

Set Several Pins to GPIO function

Set pins GPIO0, GPIO1, GPIO10 to GPIO function.

Set a Group of Pins to a Specified Function

Set a group of pins, whose group-name is UART0_X1, to UART0 function. Actually, the group includes pins GPIO50 and GPIO51.

Refer to Function-group Table in appendix.

Pin Configuration Nodes

1. bias-disable

• description

Disable any pin bias on the pin.

• argument

The argument is ignored.

• usage

2. bias-high-impedance

• description

The pin will be set to a high impedance mode, also know as "third-state" (tri-state) or "high-Z" or "floating".

• argument

The argument is ignored.

• usage

3. bias-pull-up

• description

The pin will be pulled up.

• argument

The argument is ignored.

• usage

4. bias-pull-down

• description

The pin will be pulled down.

• argument

The argument is ignored.

• usage

5. drive-open-drain

• description

The pin will be driven with open drain (open collector) which means it is usually wired with other output ports which are then pulled up with an external resistor. Setting this config will enable open drain mode.

• argument

The argument is ignored.

• usage

6. drive-strength-microamp

• description

The pin will sink or source at most the current passed as argument.

• argument

The argument is in uA.

See linux/kernel/include/dt-bindings/pinctrl/sppctl-config-sp7350.h for selectable argument.

• usage

7. input-enable

• description

Enable the pin's input.

• argument

The argument is ignored.

• usage

8. input-disable

• description

Disable the pin's input.

• argument

The argument is ignored.

• usage

9. input-schmitt-enable

• description

This will configure an input pin to run in Schmitt-trigger mode.

• argument

The argument is ignored.

• usage

10. input-schmitt-disable

• description

This will disable the pin's Schmitt-trigger mode.

• argument

The argument is ignored.

• usage

11. output-enable

• description

This will enable the pin's output mode without driving a value there.

• argument

The argument is ignored.

• usage

12. output-disable

• description

This will disable the pin's output mode.

• argument

The argument is ignored.

• usage

13. output-high

• description

This will configure the pin as output and drive high level on the line.

• argument

The argument is ignored.

• usage

14. output-low

• description

This will configure the pin as output and drive low level on the line.

• argument

The argument is ignored.

• usage

15. sunplus,input-invert-enable

• description

This will invert the pin's input value. High level as 0, Low level as 1.

• argument

The argument is ignored.

• usage

16. sunplus,output-invert-enable

• description

This will invert the pin's output value. 1 as low level, 0 as high level.

• argument

The argument is ignored.

• usage

17. sunplus,input-invert-disable

• description

This will normalize the pin's input value. High level as 1, Low level as 0.

• argument

The argument is ignored.

• usage

18. sunplus,output-invert-disable

• description

This will normalize the pin's output value. 1 as high level, 0 as low level.

• argument

The argument is ignored.

• usage

19. sunplus,bias-strong-pull-up

• description

The pin will be pulled up strongly.

• argument

The argument is ignored.

• usage

DTS Files

Device-tree source files of SP7350 are located in linux/kernel/arch/arm64/boot/dts/sunplus/.

Here lists all files for SP7350 boards:

Example

Voltage Mode Select

For 1.8V/3.0V Dual Voltage IO (DVIO) pins, we need to select their voltage in pinctrl top node in DTS file. For example,

In this example, DVIO groups 0 and 1 are configured to operate at 1.8V, while DVIO AO group 0 is designated with a voltage setting of 1.8V. Conversely, DVIO AO groups 1 and 2 are specifically set to operate at 3.0V. It is crucial to note that in the absence of a specified selection, the default voltage for these groups is set to 3.0V.

GPIO

SP7350 has 106 general purpose IO (GPIO) pins. Most of them are multiplexed with other special function pins. This section explains how to modify device-tree source file to set up GPIO pins as digital input or output pins.

Define GPIO in device-tree source file

Every single device has a node in device-tree source (dts) file in Linux. Property pinctrl-0 (or pinctrl-1, pinctrl-2,… if a device has more states) is used to point at pin configuration node within pin controller (node pinctrl@f8800080 in SP7350). Pin configuration nodes (sub-nodes in node pinctrl@f8800080 ) define the actual pins assignment.

Users need to add properties pinctrl-names and pinctrl-0 to a node (device) in device-tree source file to set up GPIOs as digital input or output pins for a device . For example:

where property pinctrl-0 sets up pins of uphy@f80bd000 device for "default" state. It is a handle (an address) to sub-node of pin-controller node.

Property typec-gpios defines one GPIO pin to GPIO98 of pin controller. Linux driver can get GPIO descriptors using the property. pctl is a handle (an address) to pin controller.

The following device-tree source of SP7350 shows definitions of sub-node pinmux_typec-pins of node pinctrl@f8800080.

Setting GPIO Characteristics

GPIO pins' characteristics, such as setting them to high, low, or configuring additional features, can also be directly specified within the pin node. For instance, we extend the previous example to add GPIO0 and GPIO1 and configure them as input and output, respectively. We introduce the extra_gpio_pins node label after typec_pins:

Add extra_gpio-pins node and label as shown below:

In the extra_gpio-pins node, GPIO0 is configured as an input with Schmitt trigger. Meanwhile, GPIO1 is configured as an output set to low, with a specified drive strength.

Special Function Pins

Some devices pins of SP7350 are multiplexed to specified pin-group of SP7350. This section explains how to modify device-tree source file to enable pins of those devices.

Every device should have a node in device-tree source (dts) file in Linux. Property pinctrl-0 (or pinctrl-1, pinctrl-2,… if a device has more states) is used to point at pin configuration node within pin controller (node pinctrl@f8800080 in SP7021). Pin configuration nodes (sub-nodes in node pinctrl@f8800080 ) define the actual pins assignment. For examples:

pinmux

1. eMMC device:

Pins of eMMC of SP7350, [D5, D3, D4, D0, D1, CLK, D2, D7, D6, CMD, DS], can be multiplexed to pin-group GPIO [20, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37].

To set up eMMC pins, users need to add properties pinctrl-names and pinctrl-0 to eMMC node mmc@f8003b00 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_emmc-pins of node pinctrl@f8800080.

String“EMMC” is defined for the only pin-group of eMMC which is mapped to GPIO [20, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37]. Refer to "Function-group Table" in Appendix.

2. GMAC

Pins of GMAC of SP7350, [RXC, RXDV, RXD0, RXD1, RXD2, RXD3, TXC, TXEN, TXD0, TXD1, TXD2, TXD3, MDC, MDIO], can be multiplexed to pin-group GPIO [3, 4, 5, 6, 13, 14, 10, 11, 7, 8, 15, 16, 9, 12].

To set up GMAC pins, users need to add properties pinctrl-names and pinctrl-0 to GMAC node stmmac@f8103000 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_gmac-pins of node pinctrl@f8800080.

String“GMAC_RGMII” is defined for the pin-group of GMAC which is mapped to GPIO [3, 4, 5, 6, 13, 14, 10, 11, 7, 8, 15, 16, 9, 12]. Refer to "Function-group Table" in Appendix.

3. SD Card

Pins of SD card of SP7350, [D1, D0, CLK, CMD, D3, D2], can be multiplexed to pin-group GPIO [38, 39, 40, 41, 42, 43].

To set up SD card pins, users need to add properties pinctrl-names and pinctrl-0 to SD card node mmc@f8003e80 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_sdcard-pins of node pinctrl@f8800080.

String“SD_CARD” is defined for the pin-group of SD card which is mapped to GPIO [38, 39, 40, 41, 42, 43]. Refer to "Function-group Table" in Appendix.

4. SDIO

Pins of SDIO of SP7350, [D1, D0, CLK, CMD, D3, D2], can be multiplexed to pin-group GPIO [44, 45, 46, 47, 48, 49].

To set up SDIO pins, users need to add properties pinctrl-names and pinctrl-0 to SDIO node sdio@f8008400 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_sdio-pins of node pinctrl@f8800080.

String“SDIO” is defined for the pin-group of SDIO which is mapped to GPIO [44, 45, 46, 47, 48, 49]. Refer to "Function-group Table" in Appendix.

5. SPI-NOR Flash

Pins of SPI-NOR flash of SP7350, [D2, CLK, D1, D3, CSB, D0], can be multiplexed to pin-group GPIO [21, 22, 23, 24, 25, 26].

To set up pins of SPI-NOR flash, users need to add properties pinctrl-names and pinctrl-0 to SPI-NOR flash node spinor@f8000b00 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_spi_nor-pins of node pinctrl@f8800080.

String“SPI_FLASH” is defined for the pin-group of SPI-NOR FLASH which is mapped to GPIO [21, 22, 23, 24, 25, 26]. Refer to "Function-group Table" in Appendix.

6. SPI-NAND Flash

Pins of SPI-NAND flash of SP7350, [D0, D2, CLK, D1, D3, CSB], can be multiplexed to either pin-group GPIO [30, 31, 32, 33, 34, 35] or pin-group GPIO [21, 22, 23, 24, 25, 26].

To set up pins of SPI-NAND flash, users need to add properties pinctrl-names and pinctrl-0 to SPI-NAND flash node spinand@f8002b80 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_spi_nand-pins of node pinctrl@f8800080.

String “SPI_NAND_X1” is defined for the pin-group 1 of SPI-NAND flash which is mapped to GPIO [30, 31, 32, 33, 34, 35]. Users can also use string “SPI_NAND_X2” for the pin-group 2 which is mapped to GPIO [21, 22, 23, 24, 25, 26]. Refer to "Function-group Table" in Appendix.

7. 8-bit NAND Flash

Pins of 8-bit NAND flash of SP7350, [RDY0, WP_B, CE_B, RE_B, CLE, ALE, WE_B, D0, D1, D2, D3, D4, D5, D6, D7], can be multiplexed to pin-group GPIO [20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36].

To set up 8-bit NAND FLASH pins, users need to add properties pinctrl-names and pinctrl-0 to 8-bit NAND flash node paranand@f8120000 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_para_nand-pins of node pinctrl@f8800080.

String“PARA_NAND” is defined for the pin-group of 8-bit NAND flash which is mapped to GPIO [20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36]. Refer to "Function-group Table" in Appendix.

8. UART0

Pins of UART0 of SP7350, [TXD, RXD], can be multiplexed to either pin-group GPIO [50, 51] or pin-group GPIO [68, 69].

To set up UART0 pins, users need to add properties pinctrl-names and pinctrl-0 to UART0 node serial@f8801900 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_uart0-pins of node pinctrl@f8800080.

String“UART0_X1” is defined for the pin-group 1 of UART0 which is mapped to GPIO [50, 51]. Users can also use string “UART0_X2” is defined for the pin-group 2 which is mapped to GPIO [68, 69]. Refer to "Function-group Table" in Appendix.

9. UART1

Pins of UART1 of SP7350, [TXD, RXD], can be multiplexed to either pin-group GPIO [52, 53] or pin-group GPIO [64, 65]. Flow-control pins of UART1 of SP7350, [RTS, CTS], can be multiplexed to either pin-group GPIO [54, 55] or pin-group GPIO [66, 67].

To set up UART1 pins, users need to add properties pinctrl-names and pinctrl-0 to UART1 node serial@f8801980 in device-tree source file. For example:

If flow-control is needed, for example:

The following device-tree source of SP7350 shows definition of sub-nodes pinmux_uart1-pins and pinmux_uart1_fc-pins of node pinctrl@f8800080.

String“UART1_X1” is defined for the pin-group 1 of UART1 which is mapped to GPIO [52, 53]. Users can also use string“UART1_X2” for the pin-group 2 which is mapped to GPIO [64, 65].

String "UART1_FC_X1" are defined for the pin-groups 1 of flow-control of UART1 which is mapped to GPIO [54, 55]. Users can also use string "UART1_FC_X2" for the pin-groups 2 which is mapped to GPIO [54, 55]. Refer to "Function-group Table" in Appendix.

10. I2C0

Pins of I2C0 of SP7350, [CLK, DATA], can be multiplexed to either pin-group GPIO [68, 69] or pin-group GPIO [54, 55].

To set up I2C0 pins, users need to add properties pinctrl-names and pinctrl-0 to I2C0 node i2c@f8828000 in device-tree source file. For example:

The following device-tree source of SP7350 shows definition of sub-nodes

pinmux_i2c_combo0-pins of node pinctrl@f8800080.

String“I2C_COMBO0_X1” is defined for the pin-group 1 of I2C0 which is mapped to GPIO [68, 69]. Users can also use string“I2C_COMBO0_X1” for the pin-group 2 of I2C0 which is mapped to GPIO [54, 55]. Refer to "Function-group Table" in Appendix.

11. PWM

PWM0 of SP7350 can be multiplexed to either pin-group GPIO [78] or pin-group GPIO [58]. PWM1 can be multiplexed to either pin GPIO [79] or GPIO [59]. PWM2 can be multiplexed to either pin-group GPIO [60] or pin-group GPIO [92]. PWM3 can be multiplexed to either pin-group GPIO [61] or pin-group GPIO [93].

To set up PWM pins, users need to add properties pinctrl-names and pinctrl-0 to PWM node pwm@f8800d80 in device-tree source file. For example, set up PWM0:

Or, for example, set up PWM0, PWM1, PWM2, PWM3:

The following device-tree source of SP7350 shows definitions of sub-nodes

pinmux_pwm0-pins, pinmux_pwm1-pins, pinmux_pwm2-pins, pinmux_pwm3-pins

of node pinctrl@f8800080.

String“PWM0_X1” is defined for the pin-group 1 of PWM0 which is mapped to GPIO [78]. Users can also use string“PWM0_X2” for pin group 2 which is mapped to GPIO [58].

String“PWM1_X1” is defined for the pin-group 1 of PWM1 which is mapped to GPIO [79]. Users can also use string“PWM1_X2” for pin group 2 which is mapped to GPIO [59].

String“PWM2_X1” is defined for the pin-group 1 of PWM2 which is mapped to GPIO [60]. Users can also use string“PWM2_X2” for pin group 2 which is mapped to GPIO [92].

String“PWM3_X1” is defined for the pin-group 1 of PWM3 which is mapped to GPIO [61]. Users can also use string“PWM3_X2” for pin group 2 which is mapped to GPIO [93].

Refer to "Function-group Table" in Appendix.

pinconf

1. One Configuration to All Pins.

Pin configuration will be applied to all pins included by property "pins" or "groups". For example:

"drive-strength-microamp = <SPPCTRL_DVIO_DRV_IOH_15200_IOL_18700UA>;" indicates that setting drive strength to 15.2mA on GPIO50 and GPIO51 included by group "UART0_X1".

2. Different Configurations to Different Pins.

If users want to set different drive strength on GPIO50 and GPIO51 respectively，do as below:

Other supported pin configurations are supposed to be configured in the same way.

Here lists some examples of pin configuration on sp7350-ev.dts:

1. SD card with typical drive source current 17.7mA (Min: 6.5mA, Max: 34.6mA) for DVIO.

2. SDIO with typical drive source current 17.7mA (Min: 6.5mA, Max: 34.6mA) for DVIO.

3. GMAC

• TXD0(GPIO7), TXD1(GPIO8), TXC(GPIO10), TXEN(GPIO11), TXD2(GPIO15), TXD3(GPIO16) with typical drive source current 16.4mA (Min: 11.3mA, Max: 21.6mA) for GPIO.

• RXC(GPIO3), RXDV(GPIO4), RXD0(GPIO5), RXD1(GPIO6), RXD2(GPIO13), RXD3(GPIO14) with typical drive source current 8.2mA (Min: 5.7mA, Max: 10.8mA) for GPIO.

• MDC(GPIO9), MDIO(GPIO12) with typical drive source current 8.2mA (Min: 5.7mA, Max: 10.8mA) for GPIO.

4. eMMC with typical drive source current 17.7mA (Min: 6.5mA, Max: 34.6mA) for DVIO.

5. I2C0 with typical drive source current 15.2mA (Min: 5.6mA, Max: 29.7mA) for DVIO.

6. I2C1 with typical drive source current 15.2mA (Min: 5.6mA, Max: 29.7mA) for DVIO.

7. I2C2 with typical drive source current 15.2mA (Min: 5.6mA, Max: 29.7mA) for DVIO.

8. I2C3 with typical drive source current 9.9mA (Min: 6.8mA, Max: 13.0mA) for GPIO.

9. I2C6 with typical drive source current 16.4mA (Min: 11.3mA, Max: 21.6mA) for GPIO.

10. I2C7 with typical drive source current 9.9mA (Min: 6.8mA, Max: 13.0mA) for GPIO.

11. UART0 with typical drive source current 15.2mA (Min: 5.6mA, Max: 29.7mA) for DVIO.

12. UART1 with typical drive source current 15.2mA (Min: 5.6mA, Max: 29.7mA) for DVIO.

13. UART2 with typical drive source current 15.2mA (Min: 5.6mA, Max: 29.7mA) for DVIO.

14. UART3 with typical drive source current 15.2mA (Min: 5.6mA, Max: 29.7mA) for DVIO.

15. UADBG with typical drive source current 6.6mA (Min: 4.5mA, Max: 8.6mA) for GPIO.

16. UART6 with typical drive source current 6.6mA (Min: 4.5mA, Max: 8.6mA) for GPIO.

17. UART7 with typical drive source current 6.6mA (Min: 4.5mA, Max: 8.6mA) for GPIO.

Refer to Driving-strength Table of GPIO and Driving-strength Table of DVIO in Appendix.

Appendix

List of Support Properties

Driving-strength Table of GPIO

Driving-strength Table of DVIO

Function-group Table