i-boot (ROM code)

i-boot (internal boot code) is stored in the chip's internal mask ROM. Upon power-on reset, when the system initializes, the program counters of all CPUs (four ARM Cortex A55) are set to point to the entry point address of the i-boot program. Once the power-on reset deasserts, the CPUs start executing from the entry point address of the i-boot program. i-boot first initializes the CPU, sets up all interrupt vectors, initializes the stack, initializes the cache, configures serial ports, sets timers, and more. After initialization, it loads x-boot from external storage devices into SRAM and executes it.

Features

i-boot has the following features:

Output log at UART0 at 115,200 bps.
UART0 pins can be turned off by OTP bit.
Read IV_MX[6..3] pins to decide boot-device.
Support 5 boot-devices: SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card, USB flash drive (on either USB2.0 or USB3.0 port)
Support secure-boot.
1. Verify digital signature of x-boot image.
2. Decrypt x-boot image.
Secure-boot is enabled by OTP bit.
Support warm-boot (wake up from deep-sleep mode).
Support peripheral-reset signal (output from G_MX2).

Main flow

Device drivers

Drivers	Features
8-bit NAND	First block of 8-bit NAND flash should contain Sunplus Boot Profile Header. Support reading 1K60 ECC sectors. x-boot image should be stored in 1K60 ECC sectors. Set MS control of pins of 8-bit NAND flash. Read cycle-time is 240 nS.
eMMC	x-boot image should be stored at Boot Area Partition 1. Set MS control of pins of eMMC device. Bus clock is 25 MHz.
SPI-NAND	First block of SPI-NAND flash should contain Sunplus Boot Profile Header. Support reading 1K60 ECC sectors. x-boot image should be stored in 1K60 ECC sectors. Support X1 and X2 position of SPI-NAND. Set MS control-bit of pins of SPI-NAND flash. Bus clock is 11.2 MHz.
SD card	x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN. File ISPBOOOT.BIN should be stored root directory of first partition of the SD card. First partition of the SD card should be FAT32 or FAT16 format. Bus clock is 5 MHz.
USB2.0 Host	x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive. First partition of the USB flash drive should be FAT32 or FAT16 format. Support high-speed read operation only
USB3.0 Host	x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive. First partition of the USB flash drive should be FAT32 or FAT16 format. Support high-speed read operation only

Boot core and other cores

CPU core 0 is the boot core and is responsible for booting. It is responsible for all boot processes from i-boot to Linux. CPU core 1, 2 and 3 spin (enter wfe mode) after initializing itself until core 0 wake up them.

Run Control of CPU Pen (at bootcompat session) :

CPU_WAIT_INIT_VAL (0xffffffff) // CPU waiting (spinning)

CPU_WAIT_A64_VAL (0xfffffffe) // CPU goes to A64

x (address other than above) // CPU goes to x

Bootstrap pins of SP7350

State of bootstrap pins of SP7350 will be read into bootstrap register (G0.31) at the moment that power-on reset is released. Refer to definition of boot-strap pins of SP7350 below:

Boot-strap pins of SP7350							Boot devices
MX6	MX5	MX4	MX3	MX2	MX1	MX0	Boot devices
1	1	1	1	1	x	x	eMMC boot
1	1	1	0	1	x	x	SPI-NAND boot
1	1	0	1	1	x	x	USB boot
1	1	0	0	1	x	x	SDC boot
1	0	1	1	1	x	x	SPI-NOR
1	0	0	0	1	x	x	8-bit NAND

Note:

If MX1 = 0, JTAG interface of CA55 of SP7350 will be enabled.
If MX2 = 0, SP7350 will enter test mode. Always set to 1 for normal operation.

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