5.3 Plus1 7021 System on Chip Introduction

This chapter uses the Plus1 7021 chip with independent intellectual property rights of Sunplus Technology as the SOC system practice platform, and integrates the digital tube display IP of the previous chapter into the SOC system as shown below; due to the need to match the FPGA daughter board and test expansion board , So the platform connection is shown below:

The corresponding board-level connection reference schematic is as follows

Note when using:

Three 50 PIN sockets U20B/U20A/J17 on the SP7021 motherboard are used to expand the FPGA daughter board;

1: U20A on the motherboard is connected to J1 of the FPGA daughter board (Pin pins correspond to one, such as 1-1 ...), and the 42 pin IO of FPGA (Bank 35 with 3.3V level) is extended through J17 for users use

2: U20B on the motherboard is connected to J2 of the FPGA daughter board (Pin pins correspond to one, such as 1-51 ...), providing the data transmission channel between the Plus1 7021 main chip on the motherboard and the FPGA

The realization of the SOC system is divided into two parts: the realization of the system hardware platform and the realization of the system software platform and will be introduced in subsequent sections.