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Field Name | Bit | Access | Description |
ReserveReserved | 15:1 | RO | Reserved |
stc_64 | 0 | RW | STC counter Bit 64(MSB) of the 65-bit STC counter. Note: Writing this register will also clear stc counter from 63 to bit 0 no matter the written value is 0 or 1 and written value will be used by stc counter. |
12.3 STC pre-scaling Register (stc divisor)
Address: 0x9C00060C
Reset: 0x04AF
Field Name | Bit | Access | Description |
src | 15 | RW | The trigger clock source of STC counter 0: System clock(default) 1: Divided external clock, please refer to stc config register. |
stc prescaler | 14:0 | RW | STC reload value When the register stc prescaler value changes, STC pre- scaling will respond to the change at once. CLKstc and CLKsys is: CLKstc=CLKsys/(stc prescaler+1) |
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Field Name | Bit | Access | Description |
ReserveReserved | 15:8 | RO | Reserved |
rtc_23_16 | 7:0 | RW | RTC counter |
12.6 RTC Divider Register (rtc divisor)
Address: 0x9C000618
Reset: 0x0059
Field Name | Bit | Access | Description |
ReserveReserved | 15:14 | RO | Reserved |
rtc_prescaler | 13:0 | RW | RTC Prescaler rtc prescaler is a 14-bit pre-scaling value used to generate the clock for the RTC counter. STC clock is divided by this pre-scaler to generate trigger of the RTC counter. The relationship of CLKrtc and CLKstc is: CLKrtc = CLKstc / (rtc prescaler + 1) When rct prescaler value changes, rtc pre scaling will respond to the change immediately. |
12.7 External reference clock dividor (stc config)
Address: 0x9C00061C
Reset:
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0x0000
Field Name | Bit | Access | Description |
ReserveReserved | 15:8 | RO | Reserved |
ext_div | 7:0 | RW | External Divider STC External clock dividor for STC. External clock (or crystal input) is divided by this factor and the divided result may be used as STC reference clock. When stc config changes, the dividor will not respond until dividor counter reaches 0. The relationship between the external clock and the STC trigger clock is: External divided clock = External clock / (2 * (ext div+1)) To setup STC at 90kHz for external 27MHz reference, please set stc config = 0x0000, (27MHz div by 2*1 = 13.5MHz) stc prescaler = 0x95,(13.5MHz div by 150 = 90kHz) |
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Field Name | Bit | Access | Description |
SRC | 15:14 | RW | Timer0 trigger source 0x0: CLKsys (system clock)(default) 0x1: CLKstc (STC pre-scaling counter wrap-around ) 0x2: CLKrtc (RTC pre-scaling counter wrap-around) 0x3: CLK timer1(timer1 wrap-around signal) |
RPT | 13 | RW | Timer0 Repeat operation 0: One-shot operation(default). In this mode, timer will stop and clear GO(bit-11) automatically when the register tm0 count reaches 0. 1: Repeat operation. In this mode, timer0 reload will be reloaded into tm0 count when the register tm0 count reaches 0. |
ReserveReserved | 12 | RO | Reserved |
GO | 11 | RW | Timer0 start/stop control 0: Timer0 paused(default); Timer0 counter value will be kept in this state. 1: Timer0 free-running |
ReserveReserved | 10:0 | RO | Reserved |
12.9 Timer0 Counter register (timer0 cnt)
Address: 0x9C000624
Reset: 0x0000
Field Name | Bit | Access | Description |
tm0_countReserverd | 15:11 | RO | Reserved |
tm0_count | 10:0 | RW | Timer0 Count Timer0 1611-bit counter value. When timer0 is activated, this counter will count down to zero when triggered by specified clock source. When tm0 count reaches 0 and trigger asserts, timer0 interrupt will be asserted. |
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Field Name | Bit | Access | Description |
SRC | 15:14 | RW | Timer1 trigger source 0x0: CLKsys (system clock)(default) 0x1: CLKstc (STC pre-scaling counter wrap-around ) 0x2: CLKrtc (RTC pre-scaling counter wrap-around) 0x3: CLK timer0(from timer0 wrap-around signal) |
RPT | 13 | RW | Timer1 Repeat operation 0: One-shot operation(default). In this mode, timer will stop and clear GO(bit-11) automatically when the register tm1 count reaches 0. 1: Repeat operation. In this mode, the register timer1 reload will be reloaded into tm1 count when tm1 count reaches 0. |
Reserve | 12 | RO | Reserved |
GO | 11 | RW | Timer1 start/stop control 0: Timer1 paused(default); Timer1 counter value will be kept in this state . 1: Timer1 free-running |
Reserve | 10:0 | RO | Reserved |
12.11 Timer1 Counter register (timer1 cnt)
Address: 0x9C00062C
Reset: 0x0000
Field Name | Bit | Access | Description |
Reserved | 15:11 | RO | Reserved |
tm1_count | 1510:0 | RW | Timer1 Count Timer1 1611-bit counter value. When timer1 is activated, this counter will count down to zero when triggered by specified clock source. |
12.12 Watchdog Timer Control register (timerw ctl)
Address: 0x9C000630
Reset: 0x0000
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Field Name | Bit | Access | Description |
stc_47_32 | 15:0 | RW | STC counter Bit 47-32 of the 65-bit STC counter. |
12.15 STC Counter Register (stc 63 48)
Address: 0x9C00063C
Reset: 0x0000
Field Name | Bit | Access | Description |
stc_63_48 | 15:0 | RW | STC counter Bit 63-48 of the 65-bit STC counter. |
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Field Name | Bit | Access | Description |
ReserveReserved | 15:6 | RO | Reserved |
SRC | 5:2 | RW | Timer2 trigger source selection 0x0: System clock(default) 0x1: STC trigger clock(STC pre-scaling counter wrap- around) 0x2: RTC trigger clock(RTC pre-scaling counter wrap- around) 0x3: External clock (reference to stc config ) 0x4: CLK timer3 trig (from timer3 trigger signal) 0x5: CLK timer3 wrap (from timer3 wrap-around signal) others: System clock |
RPT | 1 | RW | timer2 one-shot/continuous operation 0: One-shot operation(default). In this mode, timer will stop and clear GO(bit-0)automatically when tm2 count reaches 0. 1: Continuous operation. In this mode, the register tm2 reload will be reloaded into tm2 count when register tm2 count reaches 0. |
GO | 0 | RW | GO: timer2 run/stop operation 0: Timer2 paused(default). pre scaler counter and tm2 counter will keep their value in this state. 1: Timer2 running |
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Field Name | Bit | Access | Description |
timer2_reload | 15:0 | RW | Timer2 16-bit reload value When tm2 count reaches 0, the value of timer2 reload will be reloaded into tm2 count with repeat mode. When timer2 reload value changes, timer2 counter operation will not respond until timer2 generates wrap-around. If user wants timer2 to generate interrupt after XXms, the register should be set (XXms / (1/CLK timer2 kHz - 1) = XXms * CLK timer2 kHz -1 ). |
12.19 Timer2 16-bit counter value (timer2 cnt)
Address: 0x9C00064C
Reset: 0x0000
Field Name | Bit | Access | Description |
timer2_cnt | 15:0 | RW | Timer2 16-bit counter value Timer2 16-bit counter value. When timer2 is activated, it will count down to zero when triggered by specified clock source. |
12.20 Timer3 Control Register (timer3 ctl)
Address: 0x9C000650
Reset: 0x0000
Field Name | Bit | Access | Description |
ReserveReserved | 15:6 | RO | Reserved |
SRC | 5:2 | RW | Timer3 trigger source selection |
RPT | 1 | RW | timer3 one-shot/continuous operation |
GO | 0 | RW | GO: timer3 run/stop operation |
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Field Name | Bit | Access | Description |
timer3_reload | 15:0 | RW | Timer3 16-bit reload value When tm3 count reaches 0, this value will be reloaded into tm3 count with repeat mode. When timer3 reload value changes, timer3 counter operation will not respond until timer3 generates wrap-around. If user wants timer3 to generate interrupt after XXms, the register should be set (XXms / (1/CLK timer3 kHz -1) = XXms * CLK timer3kHz -1 ). |
12.23 Timer3 16-bit counter value (timer3 cnt)
Address: 0x9C00065C
Reset: 0x0000
Field Name | Bit | Access | Description |
timer3_cnt | 15:0 | RW | Timer3 16-bit counter value Timer3 16-bit counter value. When timer3 is activated, it will count down to zero when triggered by specified clock source. |
12.24 Latched value (bit 15:0) of STC counter (stcl 0)
Address: 0x9C000660
Reset: 0x0000
Field Name | Bit | Access | Description |
stc_latched | 15:0 | RW | stc latched Latched STC value [15:0]. STC counter value is latched when RISC writes stcl 2 register. |
12.25 Latched value (bit 31:16) of STC counter (stcl 1)
Address: 0x9C000664
Reset: 0x0000
Field Name | Bit | Access | Description |
stc_latched | 15:0 | RW | stc latched Latched STC value [31:16]. STC counter value is latched when RISC writes stcl 2 register. |
12.26 Latched value (bit 32) of STC counter (stcl 2)
Address: 0x9C000668
Reset: 0x0000
Field Name | Bit | Access | Description |
ReserveReserved | 15:1 | RO | Reserved |
stc_latched | 0 | RO | stc latched Bit 32 of latched STC value. STC counter value is latched when RISC writes this register |
12.27 34 bit ATC counter [15:0] (atc 0)
Address: 0x9C00066C
Reset: 0x0001
Field Name | Bit | Access | Description |
atc_0 | 15:0 | RW | 34 bit ATC counter bit [15:0] Counter value is incremented at the same condition as the STC counter. |
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Field Name | Bit | Access | Description |
ReserveReserved | 15:2 | RO | Reserved |
atc_2 | 1:0 | RW | 34 bit ATC counter [33:32] |
12.30 Timer0 16-bit reload value (timer0 reload)
Address: 0x9C000678
Reset: 0x0000
Field Name | Bit | Access | Description |
tm0_reload | 15:0 | RW | Timer0 Reload Value When tm0 count reaches 0, timer0 will generate interrupt and the value of the register tm0 reload will be reloaded into tm0 count with repeat mode. |
12.31 Timer1 16-bit reload value (timer1 reload)
Address: 0x9C00067C
Reset: 0x0000
Field Name | Bit | Access | Description |
tm1_reload | 15:0 | RW | Timer1 Reload Value When tm1 count reaches 0, the value of tm1 reload will be reloaded into tm1 count with repeat mode. |