10. General Purpose Timers

10.1 Introduction

The Timer0 and Timer1 consist of 16-bit down and auto-reload counter driven by a programmable 14-bit pre-scaler. The Timer2 and Timer3 consist of a 16-bit down and auto-reload counter driven by programmable 16-bit pre-scaler. The Timer0/1/2/3 are completely independent and don't share any resource. The Timer0/1 can combine to 32-bit timer; timer2/3 can combine to 32-bit timer. This timer module also include one 20-bit watchdog timer, one 33-bit Standard Timer Counter (STC), one 34-bit Attendance Timer Counter (ATC) and one 24-bit Real Time Counter (RTC).
The control registers locate in RGST table Group12 which memory map to 0x9C000600~0x9C00067F.

10.2 Function Diagram

A generalized function diagram of Timer is shown in Figure 10-1.

Figure 10-1 Timer Functional Blocks

Timer0: A 16-bit timer.
Timer1: A 16-bit timer.
Timer2: A 16-bit timer.
Timer3: A 16-bit timer.
Watchdog Timer: A 20-bit timer
RTC counter: A 24-bit real time counter.
ATC counter: A 34-bit attendance timer counter.
STC counter: A 33-bit standard timer counter
STC_EXT: Generate STC_EXTCLK block
Register interface: The interface of timer module communication with CPU.

Note: CLKIN = 27MHz for this chip.

10.3 Timer0/Timer1 functional description

Figure 10-2 shows the timer0 and timer1 data trigger flow block diagram.

Figure 10-2 Timer0/1 Data Trigger Flow

STC_TRIG: Trigger source of STC counter. When STC pre-scaler counter reaches 0 and trigger in STC pre-scaler asserts, the signal will be asserted for a system cycle, then sent to STC/ATC counter, RTC pre-scaler and watchdog counter as trigger. The signal is registered output.
RTC_TRIG: Trigger source of RTC counter. When RTC pre-scaler counter reaches 0 and trigger (STC_TRIG) in RTC pre-scaler asserts, the signal will be asserted for a system cycle, then sent to RTC counter as trigger. The signal is registered output.
SYSCLK: System clock source.
TIMER0_WRAP: Timer0 wrap-around signal.
TIMER1_WRAP: Timer1 wrap-around signal.

10.3.1 Time Base Operation

The 2 timers provide an 16-bit down-counter. When enable, it will down-count with a reference timing signal selecting from appropriate inputs (Refer to RGST table Group 12.8 timer0_ctl and Group 12.10 timer1_ctl registers). The interrupt will be asserted a pulse (a system clock cycle) if timer0/1 counter TIMER0_CNT/ TIMER1_CNT (Refer to RGST table Group 12.9 timer0_cnt and Group 12.11 timer1_cnt registers) reaches 0 and trigger asserts.

10.3.2 Repeat mode and One Shot mode

When timer0/1 counter reaches 0, the reload value (Refer to RGST table Group 12.30 timer0_reload and Group 12.31 timer1_reload registers) will be loaded into timer0/1 counter with repeat mode. RGST table Group 12.8 timer0_ctl bit13 set 1 as repeat mode. RGST table Group 12.10 timer1_ctl bit13 set 1 as repeat mode.
The 2 timers also provide one shot operation when RGST table Group 12.8 timer0_ctl and Group 12.10 timer1_ctl bit13 set 0. In this mode, timer will stop and clear GO flag (bit-11) automatically when the timer0/1 counter reaches 0.
When timer 0/1 reload value (TIME0_RELOAD/TIME1_RELOAD in waveform) changes, which the timer 0/1 counter will not respond to the change immediately until timer0/1 counter reaches 0. Please refer to the figure 10-3.

Figure 10-3 Timer0/Timer1 Counter Repeat Mode Timing Diagram

Note: Timer0/1 counter support dynamic read/write. When Timer0/1 counter setting is change, the counter will decrease from the new setting.

10.3.3 Timer Trigger Source

The RGST table Group 12.8 timer0_ctl bit[15:14] can select timer0 trigger source. Set 0 is selected SYSCLK, set 1 is selected STC_TRIG, set 2 is selected RTC_TRIG and set 3 is selected TIMER1_WRAP. The cooresponding function control bit of timer1 is Group 12.10 timer1_ctl bit[15:14].

10.3.4 32-bit counter mode

The Timer0/1 can combine to 32-bit counter. For example, set timer0 trigger source as SYSCLK and set timer1 trigger source as TIMER0_WRAP, then the timer0+timer1 become a 32-bit counter. When timer0_count reaches 0, it will trigger TIMER0_WRAP to let timer1_count down count and timer0_reload will be reloaded into timer0_count at the same time. Repeat this action, finally the timer0+timer1 will operate like a 32-bit counter.

10.3.5 Pause mode

When paused state, timer0/1 counter operation will be disabling and all timer0/1 counter value will be kept. Set RGST table Group 12.8 timer0_ctl bit11 as 0 to come in timer0 pause state. Set RGST table Group 12.10 timer1_ctl bit11 as 0 to come in timer1 pause state.

10.4 Timer2/Timer3 functional description

Figure 10-4 shows the timer2 and timer3 data trigger flow block diagram.

Figure 10-4 Timer2/3 Data Trigger Flow

STC_TRIG: Trigger source of STC counter. When STC pre-scaler counter reaches 0 and trigger in STC pre-scaler asserts, the signal will be asserted for a system cycle, then sent to STC/ATC counter, RTC pre-scaler and watchdog counter as trigger. The signal is registered output.
RTC_TRIG: Trigger source of RTC counter. When RTC pre-scaler counter reaches 0 and trigger (STC_TRIG) in RTC pre-scaler asserts, the signal will be asserted for a system cycle, then sent to RTC counter as trigger. The signal is registered output.
SYSCLK: System clock source.
STC_EXTCLK: External clock.
TIMER2_WRAP: Timer2 wrap-around signal.
TIMER3_WRAP: Timer3 wrap-around signal.

10.4.1 Time Base Operation

The 2 timers provide an 16-bit down-counter. When enable, it will down-count with a reference timing signal selecting from appropriate inputs (Refer to RGST table Group 12.16 timer2_ctl and Group 12.20 timer3_ctl registers). The interrupt will be asserted a pulse (a system clock cycle) if timer2/3 counter TIMER2_CNT/ TIMER3_CNT (Refer to RGST table Group 12.19 timer2_cnt and Group 12.23 timer3_cnt registers) reaches 0 and trigger asserts.

10.4.2 Repeat mode and One Shot mode

When timer2/3 counter reaches 0, the reload value (Refer to RGST table Group 12.18 timer2_reload and Group 12.22 timer3_reload registers) will be loaded into timer2/3 counter with repeat mode. RGST table Group 12.16 timer2_ctl bit1 set 1 as timer2 repeat mode. RGST table Group 12.20 timer3_ctl bit1 set 1 as timer3 repeat mode.
The 2 timers also provide one shot operation when RGST table Group 12.16 timer2_ctl and Group 12.20 timer3_ctl bit1 set 0. In this mode, timer will stop and clear GO flag (bit-0) automatically when the timer2/3 counter reaches 0.
When timer 2/3 reload value (TIME2_RELOAD/TIME3_RELOAD in waveform) changes, which the timer 2/3 counter will not respond to the change immediately until timer2/3 counter reaches 0..
Note: Timer2/3 counter support dynamic read/write. When Timer2/3 counter setting is change, the counter will decrease from the new setting.

10.4.3 Timer Trigger Source

The RGST table Group 12.16 timer2_ctl bit[5:2] can select timer2 trigger source. Set 0 is selected SYSCLK, set 1 is selected STC_TRIG, set 2 is selected RTC_TRIG, set 3 is selected external clock, set 4 is selected TIMER3_TRIG and set 5 is selected TIMER3_WRAP. The cooresponding function control bit of timer1 is Group 12.20 timer3_ctl bit[5:2].

10.4.4 32-bit counter mode

The Timer2/3 can combine to 32-bit counter. For example, set timer2 trigger source as SYSCLK and set timer3 trigger source as TIMER2_WRAP, then the timer2+timer3 become a 32-bit counter. When tm2_count reaches 0, it will trigger TIMER2_WRAP to let tm3_count down count and timer2_reload will be reloaded into tm2_count at the same time. Repeat this action, finally the timer2+timer3 will operate like a 32-bit counter.

10.4.5 Pause mode

When paused state, timer2/3 counter operation will be disabling and all timer2/3 counter value will be kept. Set RGST table Group 12.16 timer2_ctl bit0 as 0 to come in timer2 pause state. Set RGST table Group 12.20 timer3_ctl bit0 as 0 to come in timer3 pause state.

10.4.6 Pre-scaling function

The Timer2/3 can set 16-bit pre-scaling value in RGST table Group 12.17 timer2_pres_value and Group 12.21 timer3_pres_value. The specified clock source is divided by this pre-scaler to generate trigger of the Timer2/3 counter. The relationship of CLK_timer2 and CLK_src is CLK_timer2 = CLK_src / (timer2_prescaler+1). Timer3 have the same formula.

10.5 STC/ATC/RTC/Watchdog

Figure 10-5 shows the data flow of STC/ATC/RTC/Watchdog.

Figure 10-5 STC/ATC/RTC/Watchdog data flow

10.5.1 STC Pre-scaler And Counter

STC (Standard Timer Counter) has a 14-bit pre-scaler and a 33-bit counter. As Figure 10-5, STC pre-scaler will divide the SYSCLK or STC_EXTCLK then generate STC_TRIG signal.
In the applications, STC_TRIG usually is a 90 kHz signal. STC Counter will increase after trigger by STC_TRIG. This is the outline of the STC counter working mode. The paragraph follows will explain the pre-scaler and counter details.

STC pre-scaler: When pre-scaler reload value changed (STC_PRES_RELOAD in the figure), pre-scaler counter will clean to 0 right now. The divider relation is STC_TRIG = SYSCLK / (stc_prescaler＋1).
STC counter: It is a 33-bit width counter. It will increase by STC_TRIG trigger. When the counter count to the max value, if STC_TRIG come again, which action will cause overflow. The STC counter support dynamic read/write, but the value maybe not precise. So for read operation add latch-read mode. The STC counter value is latched when CPU write any value to Group 12.26 stcl_2 bit32.

10.5.2 ATC Counter

ATC (Attendance Timer Counter) is a 34-bitwidth counter; it will increase by STC_TRIG trigger. When the counter count to the max value and STC_TRIG come again, the action will cause overflow. The count value registers are Group 12.27~29. This also support dynamic read/write like STC counter

10.5.3 RTC Pre-scaler And Counter

RTC (Real Time Counter) is a 24-bit width counter. RTC Pre-scaler trigger source is STC_TRIG. It is different trigger source with STC Pre-scaler/Counter. And RTC counter doesn't support latch-read mode, other feature is the same with STC Pre-scaler/Counter

10.5.4 Watchdog Counter

This is a 20-bit width counter. On unpause state (setting by command, reference the register file, default is pause), the counter will decrease when STC_TRIG trigger. The firmware can read/write the higher 16-bit of counter by Group 12.13 timerw_cnt register. Watchdog counter controlled by command which in the Group 12.12 timerw_ctl register. Use the watchdog timer to monitor the firmware behaves. Hardware will remember the command written by software. The watchdog will be paused and unlocked state after system reset. Below lists the watchdog commands.

0xAB00: Unlock timerw_cnt register write operation (the timerw_cnt value can be written).
0xAB01: Lock timerw_cnt register write operation (the timerw_cnt value can't be written).
0x3877: Pause watchdog (the timerw_cnt value will be kept).
0x4A4B: Unpause watchdog (watchdog will be actived).
0x7482: Reset watchdog flag(clear watchdog interrupt).
0xDEAF: Set timerw_cnt maximum value (0xffff) (about 11 seconds in 108MHz operation).

Be careful, when the counter decrease to 0, the interrupt will be set until the related commands be executed then clear interrupt. And the counter value will reload to the max value on next STC_TRIG trigger.

10.6 Timer Interrupts

STC_INTERRUPT_TIMERW: Watchdog interrupt flag. When watchdog counter reaches 0, the interrupt will be asserted immediately until software clear (set timerw_ctl register to 0x7482).
STC_INTERRUPT_TIMER0: Timer0 wrap-around interrupt flag. When timer0 counter reaches 0 and trigger in timer0 asserts, the interrupt will be asserted a pulse with a system cycle, registered output.
STC_INTERRUPT_TIMER1: Timer1 wrap-around interrupt. When timer1 counter reaches 0 and trigger in timer1 asserts, the interrupt will be asserted a pulse with a system cycle, registered output.
STC_INTERRUPT_TIMER2A: Timer2 trigger interrupt. Registered output, from timer2 pre-scaler. When timer2 pre-scaler counter reaches 0 and pre-trigger in pre-scaler asserts, the trigger interrupt will be asserted a pulse with a system cycle, then sent to timer2 down counter as trigger source.
STC_INTERRUPT_TIMER2B: Timer2 wrap-around interrupt. When timer2 down counter reaches 0 and trigger (STC_INTERRUPT_TIMER2A) asserts, the interrupt will be asserted a pulse with a system cycle, registered output.
STC_INTERRUPT_TIMER3A: Timer3 trigger interrupt. Registered output, from timer3 pre-scaler. When timer3 pre-scaler counter reaches 0 and pre_trigger in pre-scaler asserts, the trigger interrupt will be asserted a pulse with a system cycle, then sent to timer3 down counter as trigger source.
STC_INTERRUPT_TIMER3B: Timer3 wrap-around interrupt. When timer3 down counter reaches 0 and trigger (STC_INTERRUPT_TIMER3A) asserts, the interrupt will be asserted a pulse with a system cycle, registered output.

10.7 Registers Map

10.7.1 Registers Memory Map

Address	Group No.	Register Name	Description
0x9C000600	G12.0	stc_15_0	STC Counter Register
0x9C000604	G12.1	stc_31_16	STC Counter Register
0x9C000608	G12.2	stc_32	STC Counter Register
0x9C00060C	G12.3	stc_divisor	STC pre-scaling Register
0x9C000610	G12.4	rtc_15_0	RTC Counter Register
0x9C000614	G12.5	rtc_23_16	RTC Counter Register
0x9C000618	G12.6	rtc_divisor	RTC Divider Register
0x9C00061C	G12.7	stc_config	External reference clock divisor
0x9C000620	G12.8	timer0_ctl	Timer0 Control Register
0x9C000624	G12.9	timer0_cnt	Timer0 Counter Register
0x9C000628	G12.10	timer1_ctl	Timer1 Control Register
0x9C00062C	G12.11	timer1_cnt	Timer1 Counter Register
0x9C000630	G12.12	timerw_ctl	Watchdog Timer Control register
0x9C000634	G12.13	timerw_cnt	Watchdog Timer Counter register
0x9C000640	G12.16	timer2_ctl	Timer2 Control Register
0x9C000644	G12.17	timer2_pres_value	Timer2 16-bit pre-scaling value
0x9C000648	G12.18	timer2 reload	Timer2 16-bit reload value
0x9C00064C	G12.19	timer2_cnt	Timer2 16-bit counter value
0x9C000650	G12.20	timer3_ctl	Timer3 Control Register
0x9C000654	G12.21	timer3_pres_value	Timer3 16-bit pre-scaling value
0x9C000658	G12.22	timer3_reload	Timer3 16-bit reload value
0x9C00065C	G12.23	timer3_cnt	Timer3 16-bit counter value
0x9C000660	G12.24	stcl_0	Latched value (bit 15:0) of STC counter
0x9C000664	G12.25	stcl_1	Latched value (bit 31:16) of STC counter
0x9C000668	G12.26	stcl_2	Latched value (bit 32) of STC counter
0x9C00066C	G12.27	atc_0	34 bit ATC counter [15:0]
0x9C000670	G12.28	atc_1	34 bit ATC counter [31:16]
0x9C000674	G12.29	atc_2	34 bit ATC counter [33:32]
0x9C000678	G12.30	timer0 reload	Timer0 16-bit reload value
0x9C00067C	G12.31	Timer1 reload	Timer1 16-bit reload value

10.7.2 Registers Description

RGST Table Group 12 STC

12.0 STC Counter Register (stc 15 0)
Address: 0x9C000600
Reset: 0x0001

Field Name	Bit	Access	Description
stc_15_0	15:0	RW	STC counter Low 16-bit of the 65-bit STC counter.

12.1 STC Counter Register (stc 31 16)
Address: 0x9C000604
Reset: 0x0000

Field Name	Bit	Access	Description
stc_31_16	15:0	RW	STC counter Bit 31-16 bit of the 65-bit STC counter.

12.2 STC Counter Register (stc 64)
Address: 0x9C000608
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	15:1	RO	Reserved
stc_64	0	RW	STC counter Bit 64(MSB) of the 65-bit STC counter. Note: Writing this register will also clear stc counter from 63 to bit 0 no matter the written value is 0 or 1 and written value will be used by stc counter.

12.3 STC pre-scaling Register (stc divisor) 
Address: 0x9C00060C
Reset: 0x04AF

Field Name

Bit

Access

Description

src

15

RW

The trigger clock source of STC counter
0: System clock(default)
1: Divided external clock, please refer to stc config register.

stc prescaler

14:0

RW

STC reload value
CLKsrc(system clock or divided external clock) divided by (stc prescaler+1) will be used to trigger the STC counter.

When the register stc prescaler value changes, STC pre- scaling will respond to the change at once.
For example, sysclk clock is choosed as source clock and the relationship between

CLKstc and CLKsys is: CLKstc=CLKsys/(stc prescaler+1)
Typically STC counter is incremented at 90kHz period. Be- low we listed the frequently used prescaler values.
Sysclk ..... stc prescaler
135MHz ..... 1500-1
121.5MHz..... 1350-1
108MHz ..... 1200-1
94.5MHz ..... 1050-1
81MHz ..... 900-1
For example, the register stc prescaler should be set (1200-1 =0x04af) to generate 90kHz STC TRIG if source clock is108M.

12.4 RTC counter register (rtc 15 0)
Address: 0x9C000610
Reset: 0x0001

Field Name	Bit	Access	Description
rtc_15_ 0	15:0	RW	RTC counter Low 16-bit of the 24-bit RTC counter.

12.5 RTC counter register (rtc 23 16)
Address: 0x9C000614
Reset: 0x0000

Field Name

Bit

Access

Description

Reserved

15:8

RO

Reserved

rtc_23_16

7:0

RW

RTC counter
Bit 23-16 bit of the 24-bit RTC counter.
Note:Writing this register will also clear rtc counter [15:0](rtc 15 0)
no matter what the written value is and the written value will be used by rtc counter.

12.6 RTC Divider Register (rtc divisor)
Address: 0x9C000618
Reset: 0x0059

Field Name

Bit

Access

Description

Reserved

15:14

RO

Reserved

rtc_prescaler

13:0

RW

RTC Prescaler

rtc prescaler is a 14-bit pre-scaling value used to generate the clock for the RTC counter.

STC clock is divided by this pre-scaler to generate trigger of the RTC counter.

The relationship of CLKrtc and CLKstc is:

CLKrtc = CLKstc / (rtc prescaler + 1)

When rct prescaler value changes, rtc pre scaling will respond to the change immediately.



12.7 External reference clock dividor (stc config) 
Address: 0x9C00061C
Reset: 0x0000

Field Name

Bit

Access

Description

Reserved

15:8

RO

Reserved

ext_div

7:0

RW

External Divider STC

External clock dividor for STC. External clock (or crystal input) is divided by this factor and the divided result may be used as STC reference clock.

When stc config changes, the dividor will not respond until dividor counter reaches 0.

The relationship between the external clock and the STC trigger clock is:

External divided clock = External clock / (2 * (ext div+1))

To setup STC at 90kHz for external 27MHz reference, please set

stc config = 0x0000, (27MHz div by 2*1 = 13.5MHz)

stc prescaler = 0x95,(13.5MHz div by 150 = 90kHz)

12.8 Timer0 Control Register (timer0 ctl)
Address: 0x9C000620
Reset: 0x0000

Field Name	Bit	Access	Description
SRC	15:14	RW	Timer0 trigger source 0x0: CLKsys (system clock)(default) 0x1: CLKstc (STC pre-scaling counter wrap-around ) 0x2: CLKrtc (RTC pre-scaling counter wrap-around) 0x3: CLK timer1(timer1 wrap-around signal)
RPT	13	RW	Timer0 Repeat operation 0: One-shot operation(default). In this mode, timer will stop and clear GO(bit-11) automatically when the register tm0 count reaches 0. 1: Repeat operation. In this mode, timer0 reload will be reloaded into tm0 count when the register tm0 count reaches 0.
Reserved	12	RO	Reserved
GO	11	RW	Timer0 start/stop control 0: Timer0 paused(default); Timer0 counter value will be kept in this state. 1: Timer0 free-running
Reserved	10:0	RO	Reserved

12.9 Timer0 Counter register (timer0 cnt)
Address: 0x9C000624
Reset: 0x0000

Field Name

Bit

Access

Description

timer0_cnt

15:0

RW

Timer0 16-bit counter value

Timer0 16-bit counter value. When timer0 is activated, it will count down to zero when triggered by specified clock source.
If timer0_cnt is zero and trigger asserts, interrupt will be generated.

12.10 Timer1 Control Register (timer1 ctl)
Address: 0x9C000628
Reset: 0x0000

Field Name	Bit	Access	Description
SRC	15:14	RW	Timer1 trigger source 0x0: CLKsys (system clock)(default) 0x1: CLKstc (STC pre-scaling counter wrap-around ) 0x2: CLKrtc (RTC pre-scaling counter wrap-around) 0x3: CLK timer0(from timer0 wrap-around signal)
RPT	13	RW	Timer1 Repeat operation 0: One-shot operation(default). In this mode, timer will stop and clear GO(bit-11) automatically when the register tm1 count reaches 0. 1: Repeat operation. In this mode, the register timer1 reload will be reloaded into tm1 count when tm1 count reaches 0.
Reserve	12	RO	Reserved
GO	11	RW	Timer1 start/stop control 0: Timer1 paused(default); Timer1 counter value will be kept in this state . 1: Timer1 free-running
Reserve	10:0	RO	Reserved



12.11 Timer1 Counter register (timer1 cnt) 
Address: 0x9C00062C
Reset: 0x0000

Field Name

Bit

Access

Description

timer1_cnt

15:0

RW

Timer1 16-bit counter value

Timer1 16-bit counter value. When timer1 is activated, it will count down to zero when triggered by specified clock source.
If timer1_cnt is zero and trigger asserts, interrupt will be generated.

12.12 Watchdog Timer Control register (timerw ctl)
Address: 0x9C000630
Reset: 0x0000

Field Name

Bit

Access

Description

timerw_ctl

15:0

WO

Watchdog Timer Command

Write command to this register to control the system watchdog.

Use the watchdog timer to monitor if the firmware behaves properly.

H/W will remember the command written by soft ware.

The watchdog will be paused and unlocked state after system reset.

0xAB00: Unlock timerw cnt register write operation(the timerw cnt value can be written)

0xAB01: Lock timerw cnt register write operation(the timerw cnt value can't be written)

0x3877: Pause watchdog (the timerw cnt value will be kept)

0x4A4B: Unpause watchdog(watchdog will be actived)

0x7482: Reset watchdog flag(clear watchdog interrupt )

0xDEAF: Set timerw cnt maximum value(0xfffff), (about 11 seconds in 108MHz operation)

12.13 Watchdog Timer Counter register (timerw cnt)
Address: 0x9C000634
Reset: 0xFFFF

Field Name

Bit

Access

Description

timerw_cnt

15:0

RW

Watchdog Timer Count

Watchdog timer is a 20-bit down-counting based on CLKstc (90kHz typically).

The down-counting value is 0xfffff after reset.

This register is from bit 4 to bit 19 of the watchdog timer counter (bit 3 to bit 0 can't be read or written,

and timerw cnt [3:0] will be cleared automatically when the register is written).

When timerw cnt counts down to zero, a flag (level interrupt) will be set immediately and hen the interrupt will trigger system level reset,

but not reset internal registers of STC. To Write this register when TIMERW LOCK is 0.

12.16 Timer2 Control Register (timer2 ctl)
Address: 0x9C000640
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	15:6	RO	Reserved
SRC	5:2	RW	Timer2 trigger source selection 0x0: System clock(default) 0x1: STC trigger clock(STC pre-scaling counter wrap- around) 0x2: RTC trigger clock(RTC pre-scaling counter wrap- around) 0x3: External clock (reference to stc config ) 0x4: CLK timer3 trig (from timer3 trigger signal) 0x5: CLK timer3 wrap (from timer3 wrap-around signal) others: System clock
RPT	1	RW	timer2 one-shot/continuous operation 0: One-shot operation(default). In this mode, timer will stop and clear GO(bit-0)automatically when tm2 count reaches 0. 1: Continuous operation. In this mode, the register tm2 reload will be reloaded into tm2 count when register tm2 count reaches 0.
GO	0	RW	GO: timer2 run/stop operation 0: Timer2 paused(default). pre scaler counter and tm2 counter will keep their value in this state. 1: Timer2 running

12.17 Timer2 16-bit pre-scaling value (timer2 pres value)
Address: 0x9C000644
Reset: 0x0000

Field Name

Bit

Access

Description

timer2_pres_value

15:0

RW

Timer2 16-bit pre-scaling value

When tm2 prescaler is a 16-bit pre-scaling value for TIMER2.

The specified clock source is divided by this pre-scaler to generate trigger of the TIMER2 counter.

The relationship of CLK timer2 and CLK src is:CLK timer2 = CLK src / (timer2 prescaler[]+1)

When tmer2 pres value changes, timer2 pre-scaling will respond to the change immediately.

12.18 Timer2 16-bit reload value (timer2 reload)
Address: 0x9C000648
Reset: 0x0000

Field Name

Bit

Access

Description

timer2_reload

15:0

RW

Timer2 16-bit reload value

When tm2 count reaches 0, the value of timer2 reload will be reloaded into tm2 count with repeat mode.

When timer2 reload value changes, timer2 counter operation will not respond until timer2 generates wrap-around.

If user wants timer2 to generate interrupt after XXms, the register should be set (XXms / (1/CLK timer2 kHz - 1) = XXms * CLK timer2 kHz -1 ).


12.19 Timer2 16-bit counter value (timer2 cnt) 
Address: 0x9C00064C
Reset: 0x0000

Field Name

Bit

Access

Description

timer2_cnt

15:0

RW

Timer2 16-bit counter value

Timer2 16-bit counter value. When timer2 is activated, it will count down to zero when triggered by specified clock source.
If timer2 cnt is zero and trigger asserts, interrupt will be generated.



12.20 Timer3 Control Register (timer3 ctl) 
Address: 0x9C000650
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	15:6	RO	Reserved
SRC	5:2	RW	Timer3 trigger source selection 0x0: System clock(default) 0x1: STC trigger clock(STC pre-scaling counter wrap- around) 0x2: RTC trigger clock(RTC pre-scaling counter wrap- around) 0x3: External clock (see stc config for reference) 0x4: CLK timer2 trig (from timer2 trigger signal) 0x5: CLK timer2 wrap (from timer2 wrap-around signal) others: System clock
RPT	1	RW	timer3 one-shot/continuous operation 0: One-shot operation(default). In this mode, timer will stop and clear GO(bit-0)automatically when the register tm3 count reaches 0. 1: Continuous operation. In this mode, register tm3 reload will be reloaded into tm3 count when register tm3 count reaches 0.
GO	0	RW	GO: timer3 run/stop operation 0: Timer3 paused(default).pre scaler counter and tm3 counter will keep value in this state. 1: Timer3 running

12.21 Timer3 16-bit pre-scaling value (timer3 pres value)
Address: 0x9C000654
Reset: 0x0000

Field Name

Bit

Access

Description

timer3_pres_value

15:0

RW

Timer3 16-bit pre-scaling value

When tm3 prescaler is a 16-bit pre-scaling value for TIMER3.

The specified clock source is divided by this pre-scaler to generate trigger of the TIMER3 counter.

The relationship of CLK timer3 and CLK src is:CLK timer3 = CLK src / (timer3 prescaler[]+1)

When timer3 pres value changes, timer3 pre-scaling will respond to the change at once.

12.22 Timer3 16-bit reload value (timer3 reload)
Address: 0x9C000658
Reset: 0x0000

Field Name

Bit

Access

Description

timer3_reload

15:0

RW

Timer3 16-bit reload value

When tm3 count reaches 0, this value will be reloaded into tm3 count with repeat mode.

When timer3 reload value changes, timer3 counter operation will not respond until timer3 generates wrap-around.

If user wants timer3 to generate interrupt after XXms, the register should be set (XXms / (1/CLK timer3 kHz -1) = XXms * CLK timer3kHz -1 ).



12.23 Timer3 16-bit counter value (timer3 cnt) 
Address: 0x9C00065C
Reset: 0x0000

Field Name

Bit

Access

Description

timer3_cnt

15:0

RW

Timer3 16-bit counter value

Timer3 16-bit counter value. When timer3 is activated, it will count down to zero when triggered by specified clock source.
If timer3 cnt reaches zero and trigger asserts, interrupt will be generated.

12.24 Latched value (bit 15:0) of STC counter (stcl 0)
Address: 0x9C000660
Reset: 0x0000

Field Name

Bit

Access

Description

stc_latched

15:0

RW

stc latched

Latched STC value [15:0]. STC counter value is latched when RISC writes stcl 2 register.
The register can be written but written value is meaningless.

12.25 Latched value (bit 31:16) of STC counter (stcl 1)
Address: 0x9C000664
Reset: 0x0000

Field Name

Bit

Access

Description

stc_latched

15:0

RW

stc latched

Latched STC value [31:16]. STC counter value is latched when RISC writes stcl 2 register. 
The register can be written but written value is meaningless.

12.26 Latched value (bit 32) of STC counter (stcl 2)
Address: 0x9C000668
Reset: 0x0000

Field Name

Bit

Access

Description

Reserved

15:1

RO

Reserved

stc_latched

0

RO

stc latched

Bit 32 of latched STC value. STC counter value is latched when RISC writes this register
no matter what the written value is (written value is meaningless).



12.27 34 bit ATC counter [15:0] (atc 0) 
Address: 0x9C00066C
Reset: 0x0001

Field Name	Bit	Access	Description
atc_0	15:0	RW	34 bit ATC counter bit [15:0] Counter value is incremented at the same condition as the STC counter.

12.28 34 bit ATC counter [31:16] (atc 1)
Address: 0x9C000670
Reset: 0x0000

Field Name	Bit	Access	Description
atc_1	15:0	RW	34 bit ATC counter [31:16] Counter value is incremented at the same condition as the STC counter.

12.29 34 bit ATC counter [33:32] (atc 2)
Address: 0x9C000674
Reset: 0x0000

Field Name

Bit

Access

Description

Reserved

15:2

RO

Reserved

atc_2

1:0

RW

34 bit ATC counter [33:32]
Counter value is incremented at the same condition as the
STC counter.
Note: Writing this register will also clear atc counter [31:0] (atc 0 and atc 1)
no matte what the written value is and the written value will be used by atc counter.

12.30 Timer0 16-bit reload value (timer0 reload)
Address: 0x9C000678
Reset: 0x0000

Field Name

Bit

Access

Description

tm0_reload

15:0

RW

Timer0 Reload Value

When tm0 count reaches 0, timer0 will generate interrupt and the value of the register tm0 reload will be reloaded into tm0 count with repeat mode.
When tm0 reload value changes, timer0 counter operation will not respond at once until timer0 generates wraparound.
If user wants timer0 to generate interrupt after 10ms, the register tm0 reload should be set 0x0383(10ms/(1/90k) -1 = 10*90 -1) at CLKstc 90K.


12.31 Timer1 16-bit reload value (timer1 reload) 
Address: 0x9C00067C
Reset: 0x0000

Field Name

Bit

Access

Description

tm1_reload

15:0

RW

Timer1 Reload Value

When tm1 count reaches 0, the value of tm1 reload will be reloaded into tm1 count with repeat mode.
When tm1 reload value changes, timer1 counter operation will not respond at once until timer1 generates wraparound.
If user wants timer1 to generate interrupt after 10ms, the register tm0 reload should be set 0x0383(10ms/(1/90k) -1 = 10*90-1) at CLKstc 90K.