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This manual describes how to use serves as a guide for utilizing the C3V-W Dual EVB (Evaluation Board). The C3V-W (LPDDR4) Dual EVB consists of two comprises two subsystems: one is Master C3V-W subsystems. One is master which runs subsystem, which operates Linux software, and the other is slave which provides extra Slave C3V-W subsystem, offering additional 3.75 GiB DRAM, a NPU, and other various peripherals (including USB3, SD card, GPIO, and etc.more). Refe Please refer to the functional block diagram of the C3V-W (LPDDR4) Daul Dual EVB, . The Master C3V-W subsystem has features 8 GiB eMMC, 8 GiB LPDDR4 SDRAM, an SD card slot, USB3, and a 100M/1000M Ethernet port. On the other hand, the Slave C3V-W subsystem has includes 8 GiB eMMC, 8 GiB LPDDR4 SDRAM, an SD card slot, and USB3. The CPIO interface connect connects the AXI bus buses of two both subsystems together.

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 Table of Contents

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The picture below is a photo of the C3V-W Dual EVB.

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The following table explains brieflytable below outlines the main components and interfaces:

2. Boot Devices and Configuration

The C3V-W Dual EVB supports boot booting from SD card and eMMC for both Master and Slave C3V-W subsystems. Refer to the table below of for the selection of boot configuration switches for Master and Slave C3V-W subsystems.

Master	Slave	Boot Configuration Switch
SD Card	SD Card
SD Card	eMMC
eMMC	SD Card
eMMC	EMMC

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Refer to map below for addressing space from view of Master C3V-W when 8 GiB LPDDR4 SDRAM is used:

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The lowest lower 3.75 GiB space is mapped to the lower bottom 3.75 GiB of the 8 GiB DRAM of on the Master C3V-W subsystem. The sequential A contiguous 0.25 GiB space is allocated for devices device registers of specific to the Master C3V-W subsystem. Next The upper 4 GiB space is mapped to the upper 4 GiB of the 8 GiB DRAM of on the Master C3V-W subsystem. The A segment of 4 GiB space , starting from address 0x2 0000 0000, is mapped dedicated to the Slave C3V-W subsystem. The final 0.25 GiB space starting , commencing from address 0x3 0000 0000, is mapped to allocated for the remaining 0.25 GiB portion of the lower 4 GiB of the 4 8 GiB DRAM on The Master C3V-W subsystem.

Address space starting In this configuration, the address space beginning from 0x2 0000 0000 is mapped specifically assigned to the lowest 4 GiB space of the Slave C3V-W via subsystem through the CPIO interface. If Consequently, if the CPU of the Master C3V-W want board intends to access the DRAM of devices of on the Slave C3V-W subsystem, it must reference the base address of the Slave C3V-W is subsystem, starting from 0x2 0000 0000.

4. Setup the CPIO Interface

The CPIO interfaces are setup in x-boot for both Master and Slave C3V-W chip.

4.1 Menu config setup of x-boot

For Master C3V-W, please run make xconfig at project top directory. Refer to picture below, when menu pops up, move cursor to “CPIO Mode” and select Master.navigate to the project's top directory and execute the command:

make xconfig

In the ensuing menu, depicted in the image below, navigate the cursor to "CPIO Mode" and select "Master."

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For Slave C3V-W, please run make xconfig at project top directory. Refer to picture below, when menu pops up, move cursor to “CPIO Mode” and select Slave.similarly, please navigate to the project's top directory and execute the command:

make xconfig

In the menu displayed, as illustrated in the accompanying image below, maneuver the cursor to "CPIO Mode" and choose "Slave."

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4.2 Synchronization of the CPIO

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interfaces

To ensure seamless operation, the CPIO interfaces of both the Master and Slave C3V-W should must be initialized synchronized during initialization and training at the same time. Two pair of GPIO signal are used to synchronize the initialization and training.. This synchronization is facilitated through the exchange of GPIO signals.

GPIO Signals

Procedure

1. Master C3V-W: Initially, the Master C3V

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1. -W awaits GPIO72 to register a HIGH signal. Once received, GPIO74 is set to HIGH, signaling the commencement of CPIO initialization and training.

2. Slave C3V-W: Upon detecting a HIGH signal on GPIO96, the Slave C3V-W sets GPIO94 to HIGH and waits for GPIO94 to register a HIGH signal. Upon receiving the HIGH signal on GPIO94, the Slave C3V-W initiates CPIO initialization and training.

5. Boot Flow of Software

As normal Refer to flow chart of C3V-W system, Dual EVB below:

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The boot process follows a predefined sequence:

• Master C3V-W

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• : The boot sequence initiates with i-boot, followed by x-boot, TF-A (Trusted Firmware-A), OP-TEE (Open Portable Trusted Execution Environment), U-Boot, and

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• ultimately Linux. Throughout this sequence, the Master C3V-W subsystem undergoes a series of initialization and configuration steps to prepare for system operation.

• Slave C3V-W

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• : Conversely, upon completion of DRAM initialization, the boot process for the Slave C3V-W subsystem ceases. Unlike the Master C3V-W subsystem, it does not proceed to execute subsequent software components. However, it remains operational within the system, providing access to its devices, including DRAM, for the Master C3V-W subsystem.

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6. Log of Master and Slave C3V-W Subsystem

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[    2.569441] Run /sbin/init as init process
/etc/init.d/rcS starts...
Mounting other filesystems ...
rc.extra [bg]
sdcard boot set...
[    2.795789] remoteproc remoteproc0: powering up f800817c.remoteproc
[    2.798426] remoteproc remoteproc0: Booting fw image firmware, size 244280
[    2.799348] virtio_rpmsg_bus virtio0: rpmsg host is online
[    2.804314] remoteproc0#vdev0buffer: registered virtio0 (type 7)
[    2.810305] remoteproc remoteproc0: remote processor f800817c.remoteproc is now up
[    2.815307] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x0
[    2.826105] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x1
[    2.838487] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x2
Boot CM4 firmware by remoteproc
extra done
End of /etc/init.d/rcS

login[143]: root login on 'console'
~ # [    2.983820] fbcon: Taking over console
~ # devmem 0x2f8800000
0x00000A30
~ #

After successful booting of Linux boots up successfully, you run “devmem 0x2f8800000” to read can execute the command

devmem 0x2f8800000

to retrieve the chip ID of the Slave C3V-W. The A correctly functioning CPIO interface should yield a chip ID of 0x00000A30 for the Slave C3V-W should be 0x00000A30. It implies that CPIO is working well. This confirmation signifies the proper operation of the CPIO interface.

6.2 Log of Slave C3V-W:

Run draiminit@0xFA20859D
bootdevice=0x00000019
Built at Mar 13 2024 19:47:40
dram_init
dwc_umctl2_lpddr4_1600_SP7350_for_realchip
MT53E2G32D4_C, 2rank, FBGA=D8CJN
SDRAM_SPEED_1600
dwc_ddrphy_phyinit_main 20231212
dwc_ddrphy_phyinit_out_lpddr4_train1d2d_3200_SP7350
bootdevice:0x00000019
XBOOT_len=0x0000B278
1D IMEM checksum ok
1D DMEM checksum ok
Start to wait for the training firmware to complete v.00 !!!
End of CA training.
End of initialization.
End of read enable training.
End of fine write leveling.
End of read dq deskew training.
End of MPR read delay center optimization.
End of Wrtie leveling coarse delay.
End of write delay center optimization.
End of read delay center optimization.
End of max read latency training.
Training has run successfully.(firmware complete)
bootdevice:0x00000019
2D IMEM checksum ok
2D DMEM checksum ok
Start to wait for the training firmware to complete v.00 !!!
End of initialization.
End of 2D write delay/voltage center optimization.
End of 2D write delay/voltage center optimization.
End of 2D read delay/voltage center optimization.
End of 2D read delay/voltage center optimization.
Training has run successfully.(firmware complete)
Register programming done!!!
Register programming done!!!
dram_init_end
Done draiminit
dram test 0x00800000 - 0x00800400


---- CPIO-R slave mode Begin ----

VCO: 4.0G, PLL: 1.0G
PHY status change: 0x08000001
PHY status check Passed
CPIO Initial Finished
PHY Mode: 0x0000008D
Timer start: 0x00000000
Timer End: 0x000000B2

After completing DRAM initialization and training, it sets the Slave C3V-W subsystem proceeds to set up and connect establish the CPIO interface and then stop running. Once the interface is configured and connected, the Slave C3V-W subsystem ceases further execution and enters a stopped state.