This manual describes how to use the C3V-W Dual EVB (Evaluation Board). C3V-W (LPDDR4) Dual EVB consists of two C3V-W subsystems. One is master which runs Linux software and the other is slave which provides extra 3.75 GiB DRAM, a NPU, and other peripherals (USB3, SD card, GPIO, and etc.). Refe to functional block diagram of C3V-W (LPDDR4) Daul EVB, Master C3V-W subsystem has 8 GiB eMMC, 8 GiB LPDDR4 SDRAM, SD card, USB3 and 1000M Ethernet. Slave C3V-W subsystem has 8 GiB eMMC, 8 GiB LPDDR4 SDRAM, SD card and USB3. CPIO interface connect AXI bus of two subsystems together.
Table of Contents
1. Main Devices or Interfaces Description
The picture below is a photo of the C3V-W Dual EVB.
The following table explains briefly:
Items | Subsystem | Explanations |
1 | Global | 12V DC power input. The diameter of the DC Jack plug is 5.5mm. The power supply current of the adapter must be greater than 1A. |
2 | Global | Main-power switch. Turn down to ON, and turn up to OFF. |
3 | Slave | Pin-headers J10: For connecting I2C0 and I2C1 signals of Slave C3V-W. Pin-headers J12: For connecting SPI_CB4 signals of Slave C3V-W. Pin-headers J14: For connecting PWM (0, 1) and I2C2 signals of Slave C3V-W. |
4 | Slave | CM4 console (UA6) of Slave C3V-W. Note GND is at the most bottom pin. It is default serial port of Cortex M4. The default baud rate is 115,200. No parity and 1 stop-bit. |
5 | Slave | Main console (UA0) of Slave C3V-W. Note GND is at the most bottom pin. This is default serial port of i-boot, x-boot, Trusted Firmware-A (TF-A), U-Boot and Linux kernel. The default baud rate is 115,200. No parity and 1 stop-bit. |
6 | Slave | 8 GiB LPDDR4 SDRAM of Slave C3V-W |
7 | Global | Boot configuration switch |
8 | Slave | Jumper header J31. Plug a jumper in to supply power for burning OTP of Slave C3V-W chip. |
9 | Master | Socket of micro SD card of Master C3V-W |
10 | Slave | Type C socket of USB 3.1 Gen1 of Slave C3V-W. It supports Low/Full/High/Super speeds, supports Host, Device and DRD. Current limit of VBUS is 1A. |
11 | Slave | Slave C3V-W chip (15mm x 15mm, 526-pin, TF-BGA) |
12 | Slave | 8 GiB eMMC of Slave C3V-W |
13 | Master | RJ-45 socket of Ethernet of Master C3V-W. It supports 10M/100M/1000M speeds. |
14 | Slave | Socket of micro SD card of Slave C3V-W |
15 | Master | 8 GiB eMMC of Master C3V-W |
16 | Master | Jumper header J26. Plug a jumper in to supply power for burning OTP of Master C3V-W chip. |
17 | Master | Master C3V-W chip (15mm x 15mm, 526-pin, TF-BGA) |
18 | Master | Type C socket of USB 3.1 Gen1 of Master C3V-W. It supports Low/Full/High/Super speeds, supports Host, Device and DRD. Current limit of VBUS is 1A. |
19 | Global | Reset key. Reset CM4 and main power-domains, but does not reset RTC. |
20 | Master | CM4 console (UA6) of Master C3V-W. Note GND is at the most left pin. It is default serial port of Cortex M4. The default baud rate is 115,200. No parity and 1 stop-bit. |
21 | Master | 8 GiB LPDDR4 SDRAM of Master C3V-W |
22 | Master | Main console (UA0) of Master C3V-W. Note GND is at the most right pin. This is default serial port of i-boot, x-boot, Trusted Firmware-A (TF-A), U-Boot and Linux kernel. The default baud rate is 115,200. No parity and 1 stop-bit. |
23 | Master | Pin-headers J11: For connecting I2C0 and I2C1 signals of Master C3V-W. Pin-headers J13: For connecting SPI_CB5 signals of Master C3V-W. Pin-headers J15: For connecting PWM (0, 1) and I2C2 signals of Master C3V-W. |
2. Boot Devices and Configuration
C3V-W Dual EVB supports boot from SD card and eMMC for both Master and Slave C3V-W. Refer to table below of selection of boot configuration switches for Master and Slave C3V-W.
Master | Slave | Boot Configuration Switch |
|---|---|---|
SD Card | SD Card |  |
SD Card | eMMC |  |
eMMC | SD Card |  |
eMMC | EMMC |  |
3. Map of Addressing Space of Master C3V-W.
Refer to map below for addressing space from view of Master C3V-W when 8 GiB LPDDR4 SDRAM is used:
The lowest 3.75 GiB space is mapped to the lower 3.75 GiB of the 8 GiB DRAM of Master C3V-W. The sequential 0.25 GiB space is for devices registers of Master C3V-W. Next 4 GiB space is mapped to upper 4 GiB of the 8 GiB DRAM of Master C3V-W. The 4 GiB space starting from address 0x2 0000 0000 is mapped to Slave C3V-W. The final 0.25 GiB space starting from address 0x3 0000 0000 is mapped to the remaining 0.25 GiB of the lower 4 GiB of the 4 GiB DRAM.
Address space starting from 0x2 0000 0000 is mapped to the lowest 4 GiB space of Slave C3V-W via CPIO interface. If CPU of Master C3V-W want to access DRAM of devices of Slave C3V-W, the base address of Slave C3V-W is from 0x2 0000 0000.
4. Setup CPIO Interface
CPIO interfaces are setup in x-boot for both Master and Slave C3V-W chip.
4.1 Menu config setup of x-boot
For Master C3V-W, please run make xconfig at project top directory. Refer to picture below, when menu pops up, move cursor to “CPIO Mode” and select Master.
For Slave C3V-W, please run make xconfig at project top directory. Refer to picture below, when menu pops up, move cursor to “CPIO Mode” and select Slave.
4.2 Synchronization of CPIO interface
CPIO of Master and Slave C3V-W should be initialized and training at the same time. Two pair of GPIO signal are used to synchronize the initialization and training.
Direction | Master C3V-W | Slave C3V-W |
|---|---|---|
Slave → Master | GPIO72 (RX) | GPIO96 (TX) |
Master → Slave | GPIO74 (TX) | GPIO94 (RX) |
Master C3V waits for GPIO72 being HIGH. Set GPIO74 to HIGH and start to train CPIO after receiving HIGH of GPIO72.
Slave C3V set GPIO96 to HIGH and then wait for GPIO94 being HIGH. Start to train CPIO after receiving HIGH of GPIO94.
5. Boot Flow of Software
As normal C3V-W system, Master C3V-W runs i-boot, x-boot, TF-A, OP-TEE, U-Boot, and then Linux while Slave C3V-W stops running after it completes DRAM initialization. Master C3V-W can access any devices including DRAM in Slave C3V-W subsystem.
6. Log of Master and Slave C3V-W Subsystem
6.1 Log of Master C3V-W:
[ 2.569441] Run /sbin/init as init process /etc/init.d/rcS starts... Mounting other filesystems ... rc.extra [bg] sdcard boot set... [ 2.795789] remoteproc remoteproc0: powering up f800817c.remoteproc [ 2.798426] remoteproc remoteproc0: Booting fw image firmware, size 244280 [ 2.799348] virtio_rpmsg_bus virtio0: rpmsg host is online [ 2.804314] remoteproc0#vdev0buffer: registered virtio0 (type 7) [ 2.810305] remoteproc remoteproc0: remote processor f800817c.remoteproc is now up [ 2.815307] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x0 [ 2.826105] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x1 [ 2.838487] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x2 Boot CM4 firmware by remoteproc extra done End of /etc/init.d/rcS login[143]: root login on 'console' ~ # [ 2.983820] fbcon: Taking over console ~ # devmem 0x2f8800000 0x00000A30 ~ #
After Linux boots up successfully, you run “devmem 0x2f8800000” to read chip ID of Slave C3V-W. The chip ID of Slave C3V-W should be 0x00000A30. It implies that CPIO is working well.
6.2 Log of Slave C3V-W:
Run draiminit@0xFA20859D bootdevice=0x00000019 Built at Mar 13 2024 19:47:40 dram_init dwc_umctl2_lpddr4_1600_SP7350_for_realchip MT53E2G32D4_C, 2rank, FBGA=D8CJN SDRAM_SPEED_1600 dwc_ddrphy_phyinit_main 20231212 dwc_ddrphy_phyinit_out_lpddr4_train1d2d_3200_SP7350 bootdevice:0x00000019 XBOOT_len=0x0000B278 1D IMEM checksum ok 1D DMEM checksum ok Start to wait for the training firmware to complete v.00 !!! End of CA training. End of initialization. End of read enable training. End of fine write leveling. End of read dq deskew training. End of MPR read delay center optimization. End of Wrtie leveling coarse delay. End of write delay center optimization. End of read delay center optimization. End of max read latency training. Training has run successfully.(firmware complete) bootdevice:0x00000019 2D IMEM checksum ok 2D DMEM checksum ok Start to wait for the training firmware to complete v.00 !!! End of initialization. End of 2D write delay/voltage center optimization. End of 2D write delay/voltage center optimization. End of 2D read delay/voltage center optimization. End of 2D read delay/voltage center optimization. Training has run successfully.(firmware complete) Register programming done!!! Register programming done!!! dram_init_end Done draiminit dram test 0x00800000 - 0x00800400 ---- CPIO-R slave mode Begin ---- VCO: 4.0G, PLL: 1.0G PHY status change: 0x08000001 PHY status check Passed CPIO Initial Finished PHY Mode: 0x0000008D Timer start: 0x00000000 Timer End: 0x000000B2
After completing DRAM initialization and training, it sets up and connect CPIO interface and then stop running.