Disclaimer
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CPU: Quad ARM Cortex-A55
1.8 GHz (2.1 GHz for specific components)
Cache
L1 Cache: 32kB I-cache / 32kB D-cache
L2 Cache: 128kB
L3 Cache: 1MB
Support NEON advance SIMD architecture & Floating-point
Support DVFS
0.5GHz ~1.5GHz @0.8V 85°C
1.5GHz ~1.8GHz @TT 0.84V 85°C
1.5GHz ~1.8GHz @SS 0.94V 85°C
Support individual core power down
Support 2/4 core configurable by e-fuse (OTP)
Support maximum frequency limited by e-fuse (OTP)
Maximum limited to 1.5GHz, 1.8GHz, and 2.1 GHz
Support Coresight debug solution
JTAG interface
CTI and PMU
ETB: 1k to 4k bytes buffer size per core
NPU: AI and Parallel Processing Engine
Verisilicon VIP9000DI, with 256kB SRAM
Up to 4.5 TOPS (@900MHz) computing power
Support configurable operating frequency
Support indivudual controllable power domain.
Support OpenCL and OpenVX with Neural Network Extension
MCU: ARM Cortex-M4
Support FPU
Support 400MHz, 200MHz, 100MHz and 25MHz
Support JTAG and SWD interface
DDR SDRAM
LPDDR4-3200, DDR4-3200, DDR3-1866
2 channels, 16 bits per channel
Up to 8GB memory capacity
Support IO retention
Internal SRAM
256kB at main power domain
384kB at CM4 (AO) power domain
For CM4 operation and DRAM IO retention data
AXI DMA
Support 16 channels
Support memory-to-memory copy
Support hardware handshake for 8-bit NAND controller
AHB DMA
Support 16 channels
Support memory-to-memory copy
Support hardware handshake for I2C and SPI controllers
Boot Devices
eMMC devicce
Support both 1.8V and 3.3V IOVDD
Support SDR up to 200 MHz (only for IOVDD = 1.8V)
Support DDR up to 160 MHz (only for IOVDD = 1.8V)
SD card
Support SD 3.0
Support SDR up to 200MHz
SPI-NAND flash
Support SLC NAND only
Support up to 150Mz (only for 1.8V)
Support 1 or 2 planes 2k page-size dice
Support 1 plane 4k page-size dice
8-bit NAND flash
Support 1.8V and 3.3V
Support 2k/4k/8 page-size dice
Support synchronous mode
SPI-NOR flash
Support 1/2/4-bit mode
Support 1.8V and 3.3V
Support up to 100Mz (only for 1.8V)
In-system Programming for Flash Devices
eMMC, SPI-NAND, 8-bit NAND, and SPI-NOR
In-system programming through USB flash drives or SD cards
Security
Support AES-128/192/256 encryption and decryption ECB, CBC, CTR mode
Support RSA
256/512/1024/2048 bits encryption
modular exponentiation
Support HASH
SHA-2 256/512
SHA-3 224/256/384/512
MD5
GHASH for AES GCM mode
Support POLY 1305
Support Pseudo RNG
Support ARM TZC-400
Support secure boot
SDIO
Support SD 3.0
Support transfer rate up to 104MB/s (UHS-1)
Video and image codec
H.264/MVC, VP8 and JPEG encoding
H.264/SVC and JPEG decoding
Individual controllable power domain.
USB3.1 (Gen. 1) Interface
Compliant to USB 3.1 Gen1 with DRD
Data rate up to 5Gbps
Integrated PHY
Support 4 sets of end-points (1 control and 3 data)
USB2.0 Interface
Compliant to USB 2.0
Support OTG 1.0
Support High and Full speeds
4 in: 3 bulk/interrupt; 1 bulk/interrupt/isochronous
4 out: bulk/interrupt; 1 bulk/interrupt/isochronous
MIPI CSI RX
1 MIPI-CSI2 RX 4D1C (1.5 Gbps per lane), support 4 virtual channel
1 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel
2 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel
Shared pins with CPIO (when CPIO disable, MIPI CSI RX enable)
2 MIPI-CSI2 RX can be combined as 1 MIPI-CSI2 RX 4D1C, support 4 virtual channel
Max resolution: 2688x1944
MIPI CSI/DSI TX
One MIPI TX output for either CSI or DSI
4 lanes with 1.5Gbps per lane
DSI TX resolution up to 1920x1080
CSI TX resolution up to 3840x2880
Audio Interfaces
One bidirectional I2S
Two unidirectional I2S
One 16-channel TDM
Configurable serial clock frequency
Support 16 bit audio format
Support both master and slave mode
Compliant with the IIS/PCM standard
Ethernet Controller
Support 10/100/1000 Mbps data rate
Support RGMII and RMII interface (1.8V)
Support IEEE1588
ADC
12-bit SAR ADC with 4-channel
Sampling rate up to 1MHz
PWM
Support 12 bits resolution
Support pre-scaling factor from 1 to 512
Real-Time-Clock (RTC)
Independent Always-On power domain
64 bits free-run timer with 32.768 kHz clock input
SPI/I2C/UART
Up to seven UART interfaces
Up to six SPI interfaces (5 master, and 1 slave)
Up to ten I2C interfaces
GPIO
Support total 106 GPIOs
Support software programmable driving strength for all GPIOs
Support 60 GPIOs with 1.8V/3.3V capability
3 groups in AO-power domain
2 groups in main-power domain
Watchdog Timer
32-bit counter
Up to 223 second
Mailbox
For inter-processor communication between CA55 and CM4
RTC
32.768 kHz crystal
Semaphore
Support read lock and write unlock
Support 16 channels
Thermal Sensor
Placed at between CPU and NPU
Support two threshold temperatures (default disable)
Alarm threshold, interrupt to CPU
Shutdown threshold, for resetting all system
Multi-Function Interface (MFI) and CPIO
Selectable proprietary CPIO and MIPI CSI-RX interfaces
CPIO interface
Supports 4 data lanes for both TX and RX, provides 1.0 GiB/s bandwidth
Support hardware auto calibration
Support hardware auto and/or software programmable SWAP and CROSSOVER modes
Support data swap
Package: 15x15mm2 FCCSP
3. Power Domains
The C3V-W architecture comprises six distinct power domains, each with its dedicated power supply that can be independently activated or deactivated. Illustrated in the figure below, these domains are: RTC, CM4 (AO), CA55, NPU, Video codec, and Main power domains.
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3.1 RTC Power Domain
The RTC power domain is typically powered by either a battery or a super capacitor. Its primary component is the real-time clock (RTC), which remains powered continuously to ensure uninterrupted operation. The RTC is driven by a 32.768 kHz crystal oscillator. Additionally, this domain includes circuitry for wake-up key detection. When the wake-up key is pressed for one second, activating the CM4_WAKEUP_KEY signal to HIGH, it triggers the enablement of power to the CM4 domain.
3.2 CM4 Power Domain
The CM4 power domain, also known as the Always On (AO) power domain, remains powered continuously, facilitating the operation of CM4 and its peripherals even when other domains like CA55 and the Main-power domain are powered down. Primarily, it manages the power flow for the CA55 and Main-power domains. CM4 possesses the capability to access all devices and peripherals within the Main-power domain even in the absence of power to the CA55.
In the current implementation, during normal operation, pressing the wake-up key for one second prompts CM4 to instruct Linux and CA55 to enter the suspend-to-RAM state (STR). While in STR state, pressing the wake-up key for 0.3 seconds triggers CM4 to instruct CA55 to restore to normal operational status.
3.3 CA55 Power Domain
The CA55 power domain encompasses four Cortex A55 cores along with their L1, L2, and L3 caches. It supports Dynamic Voltage and Frequency Scaling (DVFS). The entire CA55 cluster can be powered down, and each core within CA55 can be individually deactivated. Given that CA55 is connected to the AXI bus in the Main-power domain, its operation necessitates the activation of the Main-power domain.
3.4 Main-power Domain
The Main-power domain hosts the majority of the devices and peripherals within the C3V-W system. All components within this domain are interconnected via three AXI buses. Notably, while the DDR SDRAM controller and PHY reside in the Main-power domain, the IO buffer of the PHY and DDR SDRAM chip are positioned in the CM4 power domain. This configuration ensures that the SDRAM remains in a retention state when the Main-power domain is powered off.
3.5 NPU Power Domain
The NPU's power can be individually toggled off when not in use. However, given its connection to the AXI bus in the Main-power domain, operating the NPU requires the Main-power domain to be activated.
3.6 Video-codec Power Domain
Similar to the NPU, the power supply to the video codec can be individually deactivated when not in use. Nevertheless, the video codec's operation necessitates the activation of the Main-power domain due to its connection to the AXI bus within that domain.
4. CPU, MCU, NPU and DRAM Interface
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Channel | Data Lane # | Virtual Channel # | Remarks |
|---|---|---|---|
RX0 | 2 | 2 | Not available in this package |
RX1 | 2 | 2 | Not available in this package |
RX2 | 2 | 2 | |
RX3 | 2 | 2 | |
RX4 | 2 | 2 | |
RX5 | 4 | 4 |
It's important to note that RX2 and RX3 share pins with the CPIO interface. Therefore, only one of RX2/RX3 or the CPIO interface can be active at any given time.
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