Under Construction…This document elucidates the application circuitry associated with the C3V-W. It serves as a supplementary resource to the specification of the C3V-W.
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All power sources should be managed using the CM4_PWR_EN signal. Specifically, when CM4_PWR_EN is set to LOW, all power supplies, including those for the CM4 and Main power domain, should be deactivated.
Please refer to the provided power scheme for details on power control.
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Refer to the power scheme illustrated below. All powers in the main power domain should be controlled by both CM4_PWR_EN and MAIN_PWR_EN signals. Specifically, all powers in the main power domain are only turned on when both CM4_PWR_EN and MAIN_PWR_EN are set to HIGH.
It's important to note that during cold booting, CM4_PWR_EN goest to HIGH to initiate the booting process. Therefore, the default state ofMAIN_PWR_EN (when the GPIO is not yet programmed) should be HIGH to allow the CA55 to start booting.
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Typically, MAIN_PWR_EN is controlled by a GPIO in the CM4 domain. CM4 can directly set the power of the main power domain to either on or off.
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DDR Type | Max. Clock | Max. Data Rate | Max. BW (1 ch) | Max. BW (2 ch) |
|---|---|---|---|---|
LPDDR4 | 1.600 GHz | 3200 MT/s | 6.4 GB/s | 12.8 GB/s |
DDR4 | 1.333 GHz | 2666 MT/s | 5.3 GB/s | 10.7 GB/s |
LPDDR3 / DDR3 / DDR3L | 0.933 MHz | 1866 MT/s | 3.7 GB/s | 7.5 GB/s |
Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.
5.1 Data Bus and Data Strobe Signals Wiring
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ILIM = 6800/6800 = 1.0 (A)
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Note that R218 and C247 are requested and defined by OTG specification. Do not alter their values.
The UPHY0_DRV5V_EN signal controls VBUS on/off states, generated by the OTG hardware of C3V-W.
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The MIPI-RX4 (CSI) channel supports two data and one clock lanes (2d1c) and 2 virtual channels. Each data lane can handle transmission speeds up to 1.5 Gbps, supporting a maximum resolution of 2688x1944.
15.1 MIPI-RX4 Port of C3V-W
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The MIPI-RX5 (CSI) channel has four data and one clock lanes (4d1c) and supports 4 virtual channels. Each data lane can transmit up to 1.5 Gbps, supporting a maximum resolution of 2688x1944.
16.1 MIPI-RX5 Port of C3V-W
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When CPIO is disabled, MIPI-RX2 and MIPI-RX3 are available for use. MIPI-RX2 supports 4 four data lanes and 1 one clock lane lanes (4d1c) with 4 virtual channels if MIPI-RX3 is not enabled. However, if MIPI-RX3 is enabled, both MIPI-RX2 and RX3 support 2 two data lanes and 1 one clock lane lanes (2d1c). Each data lane can handle transmit up to 1.5 Gbps, supporting a maximum resolution of 2688x1944. Please refer to the table for pin sharing between MIPI-RX2, MIPI-RX3, and CPIO.
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18. MIPI-TX
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MIPI
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TX output port that can be configured as CSI for camera output or DSI for display output. This interface provides four data and one clock lanes with data rate of 1.5Gbps per lane.
18.1 MIPI-TX Port of C3V-W
Refer to the schematic for details. MIPITX_OUTP[3:0] and MIPITX_OUTN[3:0] are differential data pairs, while MIPITX_CLKP and MIPITX_CLKN are differential clock pairs. MIPITX_AVDD18 power pin provide analog 1.8V to the MIPITX PHY. Bypass capacitors and ferrite beads on power and ground lines are recommended for stable operation.
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18.2 15-Pin Display Connector (2d2c) of Raspberry Pi
The schematic shows CON6, a 15-pin display FFC connector (1.0mm pitch) compatible with Raspberry Pi. Apart from connecting MIPITX differential-pair signals, it also connects to I2C channel 6 (I2C6) for display setup and control. The I2C signal level defined by the Raspberry Pi camera is 3.3V. Voltage translators are used to convert the I2C signal level from SYS_1V8 (1.8V) to 3.3V.
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It's recommended to include ESD protection diodes for MIPITX data and clock differential pairs.
19. CA55 JTAG Interface
The C3V-W board supports the JTAG ICE interface for Cortex A55 (CA55). This interface enables developers to perform real-time debugging by connecting to the CA55 processor's JTAG (Joint Test Action Group) interface.
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