SP7350 Application Circuits

This document elucidates the application circuits associated with the SP7350. It serves as a supplementary resource to the specification of the SP7350.

Table of Contents

1. RTC

The SP7350 comes equipped with a built-in real-time clock (RTC) module, strategically placed within an independent power domain. This module is designed to remain powered continuously by an external power source such as a Lithium battery or super capacitor. This ensures uninterrupted functionality, even when other power domains are deactivated.

1.1 Power Requirements

Operating on a mere 1.8 volts, the RTC module is notably efficient. Its internal Low Dropout Regulator (LDO) generates a 0.8-volt power supply specifically for the RTC digital core. Refer to the schematic below for recommended power pin configurations, which necessitate the inclusion of bypass capacitors on the X32K_AVDD18, VDDPST18_GPIO_RTC and VDD_RTC pins.

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1.2 32.768kHz Crystal

To work with precision, the RTC module requires connection to a 32.768 kHz crystal, alongside phase-shift circuitry, as illustrated in the schematic provided.

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1.3 RTC_1V8 Power Supply

1.3.1 RTC_1V8 Power Supply with Super Capacitor

The schematic below illustrates a sample RTC_1V8 power supply circuit that uses a super capacitor for backup power.. The circuit draws primary power from the 5V VCC source and uses a 0.47 Farad super capacitor to store energy and maintain power to the RTC during VCC interruptions in the main supply. Resistor R16 (470Ω) limits the capacitor's charging current, while diode D3 blocks reverse current flow, preventing the super capacitor from discharging back into the VCC line when the external power is unavailable. A low quiescent current 1.8V LDO regulator converts VCC_RTC to the required 1.8V (RTC_1V8) needed for RTC module operation.

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Given that the RTC_1V8 current consumption is approximately 150 µA, we can estimate the duration the RTC can operate solely on the super capacitor:

t = C× ΔV / I = 0.47 × (5 − 2) / 0.00015 = 9400 (seconds)

This equates to approximately 2 hours and 36 minutes of backup operation using only the super capacitor.

1.3.2 RTC_1V8 Power Supply with Lithium Battery

The schematic below illustrates a sample RTC_1V8 power supply circuit that uses a Lithium battery for backup power. When external power is available, the circuit draws power from the 5V VCC source. When the external source is unavailable, it automatically switches to draw power from the Lithium battery (B1). Diode D3 blocks reverse current flow, preventing the Lithium battery from feeding back into the VCC supply when external source is unavailable. Diode D4 prevents charging current from flowing into the Lithium battery when VCC is present. A low quiescent current 1.8V LDO regulator converts VCC_RTC to the necessary 1.8V (RTC_1V8) required by the RTC module.

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Given a 50 mAh Lithium battery and the same RTC current consumption of 150 µA, the estimated backup time can be calculated as:

t = Ah / I = 0.05 / 0.00015 = 333.3 (hours)

So, the RTC can operate for about 13 days and 21 hours on the Lithium battery alone.

1.4 External RTC module

If the backup duration provided by either the super capacitor or Lithium battery is not sufficient for your application, you may consider adding an external low-power RTC module, such as the NXP PCF85363A. This RTC features ultra-low power consumption, typically around 0.28 µA, enabling significantly longer backup time even with relatively small energy storage elements.

Refer to the schematic below for a typical implementation using the PCF85363A.

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With the same 50 mAh Lithium battery, the estimated backup time is:

t = Ah / I = 0.05 / 0.00000028 = 178571.4 (hours)

This corresponds to approximately 20 years, 140 days, and 11 hours of continuous operation on the Lithium battery alone.

1.5 Wake-up Key Detection

The RTC module also boasts wake-up key detection functionality. When the CM4_WAKEUP_KEY pin is maintained at a HIGH state for 1 second, the CM4_PWR_EN pin is automatically set to HIGH by internal logic, activating power to the CM4 power domain. Refer to the timing charts below for a visual representation of this process.

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Furthermore, if the CM4_WAKEUP_KEY pin remains HIGH for over 10 seconds, CM4_PWR_EN is forcibly set to LOW, effectively powering down the CM4 power domain. This functionality is depicted in the accompanying timing chart.

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In addition to its hardware capabilities, the CM4 software incorporates default functionality as outlined below:

Refer to the schematic below for an example circuitry setup. In this configuration, the CM4_WAKEUP_KEY pin is linked to a physical key. Pressing the key pulls the CM4_WAKEUP_KEY signal to HIGH, while its default state remains LOW.

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2. CM4 System

The CM4 system is equipped with an ARM Cortex M4 microcontroller and an array of interfaces, including 10 channels of I2C, 6 channels of SPI, 4 channels of PWM, 6 channels of UART, and 3 channels of audio I2S. The pins associated with these peripherals can be programmed to connect to either dual voltage IO (DVIO) pins or general-purpose IO (GPIO) pins.

Operating within its own independent power domain, the CM4 system is designed to remain functional even when the main power domain (comprising the CPU, NPU, video codec, MIPI-TX, MIPI-RX, USB3, etc. ) is powered off. The primary objectives of the CM4 system are as follows:

• Control the power on and off sequences of the main power domain.

• Communicate with Linux, running in the main power domain, via mailbox to facilitate entry into and resumption from deep-sleep mode (suspend to RAM).

• Manage peripherals and IO operations of the CM4 system, including external devices control and communication with other devices or microcontrollers.

• Monitor external events, such as signals from remote controllers and human voice commands.

2.1 Power Requirements

The CM4 system requires four distinct power sources:

• 0.8V power for the digital core and system PLL (PLLS).

• 1.8V power for the ADC, GPIO, dual voltage IO (DVIO), and VDD1 of LPDDR4 SDRAM.

• 3.0V power for DVIO.

• 1.1V power for VDDQ and VDD2 of LPDDR4 SDRAM, or alternatively, 1.5/1.35V power for VDDQ of DDR3/3L SDRAM.

All power sources should be managed using the CM4_PWR_EN signal. Specifically, when CM4_PWR_EN is set to LOW, all power supplies, including those for the CM4 and Main power domain, should be deactivated.

Please refer to the provided power scheme for details on power control.

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Refer to the schematic below for the recommended wiring of the 0.8V power supply for the digital core (VDD_AO) and system PLL (AVDD08_PLLS). It's crucial to include bypass capacitors to effectively filter high-frequency noise from the power supply lines. Additionally, for the AVDD08_PLLS power pin, it's recommended to use a ferrite bead on both the power and ground lines. This helps ensure precise operational frequency and minimizes clock jitter.

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2.2 25MHz Crystal

The CM4 system needs a 25 MHz crystal accompanied by phase-shift circuitry, as depicted in the schematic below. This clock serves as the reference for various PLLs within the system, including PLLS (the system PLL), as well as PLLC, PLLL3, PLLD, PLLN, and PLLH, all located within the main power domain.

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2.3 ADC

Featuring a four-channel, 12-bit analog-to-digital converter (ADC), the CM4 system requires a 1.8V power supply. It's recommended to incorporate a ferrite bead for power pin SAR12B_AVDD18 and separate grounding to filter out high-frequency noise, as depicted in the schematics.

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2.4 DVIO (AO_MX0 ~ AO_MX29)

The DVIO pins are grouped into three categories, each with its own power supply and bias power pins. Consult the table provided for pin grouping details, ensuring appropriate connections with bypass capacitors.

The VDDPST18_DVIO_AO_x pins (where 'x' represents 1, 2, or 3) are designated for internal bias circuitry and necessitate connection to bypass capacitors. Simultaneously, the VDDPST3018_DVIO_AO_x pins (where 'x' represents 1, 2, or 3) require connection to a power supply of either 1.8V or 3.0V, supplemented by bypass capacitors.

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2.5 GPIO, Bootstrap and RESET Pins

In addition to DVIO pins, the CM4 system includes a RESET pin, seven bootstrap pins, and nineteen GPIO pins. These pins are powered by two VDDPST18_GPIO_AO pins connected to a 1.8V power supply with bypass capacitors.

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2.5.1 GPIO (AO_MX30 ~ AO_MX48)

These pins serve as 1.8V general-purpose IO (GPIO) pins and are prefixed with "AO_" indicating their association with the Always On (CM4) power domain. For ease of reference, consult the table below to determine the corresponding GPIO number for manipulation of IO registers.

2.5.2 Bootstrap Pins (IV_MX0 ~ IV_MX6)

The seven bootstrap pins encompass a variety of functions pertaining to boot device selection, CA555 JTAG/SWD interface activation, and chip test mode activation. Refer to the table below for the definition of each bootstrap pin regarding boot device selection:

(Note: "x" indicates "don't care" value)

When IV_MX2 is set to LOW, the SP7350 enters test mode, designated for internal use only. Likewise, when IV_MX1 is set to LOW, the CA55 JTAG/SWD interface pins are activated. IV_MX0 remains unused.

Following the de-assertion of the RESET pin, these pins can be repurposed as GPIOs. Refer to the table below for the corresponding GPIO numbers for IO registers manipulation.

2.5.3 Reset Circuitry

Pulling the RESET pin to LOW initiates a reset of the CM4 system, encompassing all components such as the Cortex M4, digital core, peripherals, DVIO, and GPIO pins. The schematic indicates the use of a voltage supervisor chip responsible for monitoring the 1.8V power supply.

The RESETB signal transitions to a deasserted state (HIGH) once the 1.8V power stabilizes and is ready for operation, a condition met after a typical duration of 107 milliseconds. Conversely, if the power supply fails to stabilize within this timeframe, the RESETB signal remains asserted (LOW), ensuring that the reset process is delayed until a stable power state is achieved.

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2.5.4 Setup IO Voltage of Boot Device

The GPIO82 pin plays a crucial role in configuring the internal bias circuitry of DVIO pins utilized by boot devices. During the boot sequence execution, the i-boot (ROM code) reads the state of this pin to establish the bias circuitry of the DVIO pins associated with the boot device.

For systems utilizing a 1.8V IO boot device, it is necessary to connect the GPIO82 pin to GND through a 4.7 kΩ pull-down resistor. This configuration ensures proper setup of the bias circuitry for compatibility with the 1.8V IO boot device. Conversely, if employing a 3.3V IO boot device, it is essential to leave the GPIO82 pin open to maintain compatibility with the higher voltage requirement of the boot device.

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3. Powers for Main System

The main system encompasses all components except for the RTC module and CM4 system. This includes the ARM Cortex A55, DDR SDRAM controller, NPU (VIP9000), video codec, GMAC, USB3, USB3, MIPI-RX, MIPI-TX, eMMC, SD card, SDIO and NAND flashes controller and etc.

Refer to the power scheme illustrated below. All powers in the main power domain should be controlled by both CM4_PWR_EN and MAIN_PWR_EN signals. Specifically, all powers in the main power domain are only turned on when both CM4_PWR_EN and MAIN_PWR_EN are set to HIGH.

It's important to note that during cold booting, CM4_PWR_EN goest to HIGH to initiate the booting process. Therefore, the default state of MAIN_PWR_EN (when the GPIO is not yet programmed) should be HIGH to allow the CA55 to start booting.

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Typically, MAIN_PWR_EN is controlled by a GPIO in the CM4 domain. CM4 can directly set the power of the main power domain to either on or off.

3.1 Power Requirements for PLL, Thermal Sensor, and OTP Burning

Refer to the schematic below for the recommended power configuration. Provide a 0.8V power supply for PLLs (AVDD08_PLLC and AVDD08_PLLD) and a 1.8V power supply for the thermal sensor (TML_AVDD18) and OTP burning (OTP_1V8). Bypass capacitors are essential to filter out high-frequency noise from the power supply lines.

AVDD08_PLLC powers PLLC (the CPU PLL), PLLL3 (the CPU L3 cache PLL), PLLH (the peripheral PLL), and PLLN (the NPU PLL). Similarly, AVDD08_PLLD powers PLLD (the DRAM PLL). Both require ferrite beads on the power and ground lines for stability and reduced clock jitter.

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3.2 Power Requirements for System, Video-Codec, CA55 and NPU

The recommended power wiring for VDD (system digital core), VDD_VV (video codec), VDD_CA55 (CPU CA55), and VDD_NPU (NPU) is detailed in the schematic below. Bypass capacitors are crucial to provide a low-impedance path to ground and reduce voltage ripple when high current is drawn.

Refer to the table below for the target impedance for each power domain, ensuring optimal performance:

Each power domain operates independently and can be powered on or off individually. Note that VDD powers the system digital core, including the AXI bus and top-level components. It should be powered on first, followed by CA55, NPU, and the video codec for proper functionality.

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Additionally, the VDD_NPU_MEASURE signal, a subset of the VDD_NPU pin, serves the specific purpose of providing feedback on the VDD_NPU voltage to the DC2DC regulator for precise control.

4. GPIO and DVIO of Main System

The main system features 20 General Purpose IO (GPIO) pins and 18 Dual Voltage IO (DVIO) pins. GPIO operates at 1.8V, while DVIO offers the flexibility of operating at either 1.8V or 3.0V, accommodating various voltage requirements.

In addition to serving as IO pins, interface pins of devices within the CM4 system or main system can be configured to connect to GPIO or DVIO pins. This adaptability facilitates seamless integration, enhancing overall flexibility and functionality within the system architecture.

4.1 GPIO (G_MX0 ~ GMX19)

GPIO pins are powered by two VDDPST18_GPIO_0 and VDDPST18_GPIO_1 power pins, which should be connected to a 1.8V power supply with bypass capacitors for stable operation.

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For ease of reference, consult the table below to determine the corresponding GPIO number for manipulation of IO registers:

Moreover, the G_MX2 (GPIO2) pin fulfills a specialized role in resetting peripherals by generating a 10-millisecond LOW pulse during system reboots. A dedicated driver is incorporated into GPIO2 to manage the PER_RESET (low-active) signal effectively. Refer to the following schematics for further details.

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4.2 DVIO (G_MX20 ~ GMX37)

The DVIO pins are divided into two groups, each with its own power supply and bias power pins. Refer to the table provided for pin grouping details:

Ensure appropriate connections with bypass capacitors for stable operation. The VDDPST18_DVIO_x pins (where 'x' represents 1 or 2) are designated for internal bias circuitry, while the VDDPST3018_DVIO_x pins (where 'x' represents 1 or 2) require connection to a power supply of either 1.8V or 3.0V, supplemented by bypass capacitors.

Refer to the schematics for visual guidance.

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5. DDR SDRAM

The DDR SDRAM controller of SP7350 support five types of DDR SDRAM: LPDDR4, DDR4, LPDDR3, DDR3, and DDR3L. The maximum support speed are:

Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.

5.1 Data Bus and Data Strobe Signals Wiring

Refer to the table below for the wiring of data bus and data strobe signals for different types of DDR SDRAM.