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Disclaimer

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Channel	Data Lane #	Virtual Channel #	Remarks
RX0	2	2	Not available in this package
RX1	2	2	Not available in this package
RX2	2	2
RX3	2	2	Not available for version A chips.
RX4	2	2
RX5	4	4

It's important to note that RX2 and RX3 share pins with the CPIO interface. Therefore, only one of RX2/RX3 or the CPIO interface can be active at any given time.

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16 Electric Characteristics

16.

...

DS[3:0]

...

Source current (mA)

...

1 Absolute Maximum Ratings

Symbol

Parameter

Min.

Typ0

Max.

Min.

Typ.

Max.

Unit
V_DD33	Supply voltage 3.3V	3.0	3.63	V
V_{DD_CA55}	Supply voltage 0.85V for CA55	0.8

1.1

1.5

0.89	V
V_{DD_NPU}	Supply voltage 0.85V for NPU	0.

7

8

1

0.

1

89

1.6

1

1.1

1.6

2.2

1.1

1.7

2.3

2

2.3

3.3

4.3

2.1

3.3

4.7

3

3.4

4.9

6.5

3.2

5.0

7.0

4

4.5

6.6

8.6

4.2

6.6

9.3

5

5.7

8.2

10.8

5.3

8.3

11.7

6

6.8

9.9

13.0

6.3

9.9

13.9

7

7.9

11.5

15.1

7.4

11.6

16.2

8

9.0

13.1

17.2

8.4

13.2

18.5

9

10.2

14.8

19.4

9.4

14.8

20.8

10

11.3

16.4

21.6

10.5

16.5

23.1

11

12.4

18.1

23.7

11.5

18.1

25.4

12

13.5

19.6

25.8

12.6

19.7

27.6

13

14.7

21.3

28.0

13.6

21.4

29.9

14

15.8

22.9

30.1

14.6

23.0

32.1

15

16.9

24.6

32.3

15.7

24.6

34.4

16.2 Driving-strength Table of DVIO

...

DS[3:0]

...

Source current (mA)

...

Sink current (mA)

...

Min.

...

Typ.

...

Max.

...

Min.

...

Typ.

...

Max.

...

0

...

1.9

...

5.1

...

9.9

...

4.0

...

6.2

...

8.6

...

1

...

2.8

...

7.6

...

14.8

...

6.0

...

9.3

...

12.9

...

2

...

3.7

...

10.1

...

19.8

...

8.1

...

12.5

...

17.1

...

3

...

4.6

...

12.6

...

24.7

...

10.1

...

15.6

...

21.4

...

4

...

5.6

...

15.2

...

29.7

...

12.1

...

18.7

...

25.7

...

5

...

6.5

...

17.7

...

34.6

...

14.1

...

21.8

...

29.9

...

6

...

7.4

...

20.2

...

39.5

...

16.1

...

24.9

...

34.2

...

7

...

8.3

...

22.7

...

44.3

...

18.1

...

27.9

...

38.4

...

8

...

9.3

...

25.2

...

49.3

...

20.1

...

31.0

...

42.7

...

9

...

10.2

...

27.7

...

54.2

...

22.1

...

34.1

...

46.9

...

10

...

11.1

...

30.3

...

59.1

...

24.1

...

37.2

...

51.1

...

11

...

12.0

...

32.8

...

64.0

...

26.1

...

40.3

...

55.3

...

12

...

13.0

...

35.3

...

68.9

...

28.1

...

43.4

...

59.5

...

13

...

13.9

...

37.8

...

73.7

...

30.1

...

46.4

...

63.8

...

14

...

14.8

...

40.3

...

78.6

...

32.1

...

49.5

...

67.9

...

15

...

15.7

...

42.7

...

83.4

...

34.1

...

52.6

...

72.1

16.3 Resistance of Pull-up and down of GPIO

...

Parameter

...

Min.

...

Typ.

...

Max.

...

Unit

...

Remarks

...

R_SPU

...

1.6

...

2.1

...

3

...

kΩ

...

Resistance of strong pull up

...

R_PU

...

32

...

48

...

79

...

kΩ

...

Resistance of pull up

...

R_PD

...

30

...

44

...

65

...

kΩ

...

Resistance of pull down

16.4 Resistance of Pull-up and down of DVIO

Parameter

Min.

Typ.

Max.

Unit

Remarks

R_PU

29

35

45

kΩ

Resistance of pull up

R_PD

24

28

33

kΩ

Resistance of pull down

V
V_DD08	Supply voltage 0.8V for DRAM, video codec, chip top system, AO (Always On) and RTC power domain, and other 0.8V for Analog core power	0.72	0.88	V
V_DD18	Supply voltage 1.8V	1.72	1.98	V
V_DD11	Supply voltage 1.1V	1.06	1.17	V
V_DD30	Supply voltage 3.0V²	2.7	3.3	V
V_O33	Output voltage 3.3V	3.0	3.63	V
V_O18	Output voltage 1.8V	1.72	1.98	V
V_I33	3.3V input voltage (3.3V tolerant inputs)	3.0	3.63	V
V_I18	1.8V input voltage	1.72	1.98	V
T_J	Junction temperature	-30	120	°C
T_STG	Storage temperature	-40	150	°C

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damages to the device. Functional operations of this device at these or any other conditions above those indicated in the operational sections of this specification are not implied and the exposure to absolute maximum rating conditions for extended periods may affect the device’s reliability.

16.2 Thermal Information

Symbol	Parameter	Unit (°C/W)
θ_JA	Thermal resistance, junction to ambient (JEDEC PCB 4 Layer; Air flow = 0m/s, Ambient 85°C)	13.9
Ψ_JT	Junction-to-top characterization parameter	0.08

Note: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In application where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

16.3 ESD Ratings

Symbol	Parameters	Min.	Max.	Unit
V_ESD	Human Body Model (test Per JS-001-2017)	-2	+2	kV
V_ESD	Charge Device Mode (test Per JESD22-C101F)	-500	+500	V
I_LA	Latch-up tolerance (test Per JESD78E)	-100	+100	mA

16.4 DC Characteristics

Voltage referenced to VSS = 0V, Ta =25°C

16.4.1 3.0/1.8V DVIO Specification (3.0V Mode)

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_IH	High-level input voltage	-	1.875	-	3.3	V
V_IL	Low-level input voltage	-	0	-	0.75	V
V_OH	High-level output voltage		2.75	-	V_DD33	V
V_OL	Low-level output voltage		0	-	0.375	V
I_OZ	High-impedance state output current	V_O = 0 to V_DD30		±1³		mA
C_I	Input capacitance			5		pF

16.4.2 3.0/1.8V DVIO Specification (1.8V Mode)

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_IH	High-level input voltage	-	1.27	-	1.98	V
V_IL	Low-level input voltage	-	0	-	0.58	V
V_OH	High-level output voltage		1.45	-	1.98	V
V_OL	Low-level output voltage		0	-	0.45	V
I_OZ	High-impedance state output current	V_O = 0 to V_DD18		±1		mA
C_I	Input capacitance			5		pF

16.4.3 1.8V GPIO Specification

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_IH	High-level input voltage	-	1.17	-	V_DD18	V
V_IL	Low-level input voltage	-	0	-	0.63	V
V_OH	High-level output voltage		1.35	-	V_DD18	V
V_OL	Low-level output voltage		0	-	0.45	V
I_OZ	High-impedance state output current	V_O = 0 to V_DD18		±1		mA
C_I	Input capacitance			5		pF

16.4.4 Crystal X_IN 25MHz Specification

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
	Power for Xin 25 MHz		0.72	0.80	0.88	V
V_IH	High-level input voltage		0.70		V_DD08	V
V_IL	Low-level input voltage		0		0.30	V
C_I	Input capacitance			5		pF
R_XIN	Input impedance			13		MΩ
	Power down current			2.69	51.1	µA

16.4.5 Crystal X_IN 32.678kHzSpecification

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
	Power for Xin 32.768 kHz		1.62	1.80	1.98	V
V_IH	High-level input voltage		0.70		V_DD08	V
V_IL	Low-level input voltage		0		0.3	V
C_I	Input capacitance			5		pF
R_XIN	Input impedance			13		MΩ

16.4.6 SAR ADC Specification

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
	Power for SAR ADC		1.62	1.80	1.98	V
RS_SAR	Resolution			12		bits
ENOB	Effective number of bits			10		bits
INL_SAR	Integral nonlinearity	Fin = 10Hz Fs = 250kHz		3		LSB
DNL_SAR	Differential nonlinearity	Fin = 10Hz Fs = 250kHz		3		LSB
	Input range		0		V_DD18	V
	Power down current			4.52	46.8	µA

16.4.7 Thermal Sensor Specification

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
	ADC resolution			11		bits
	Operation temperature range		-40		125	℃
	Temperature resolution	@-10~90℃		0.2		℃
	Temperature accuracy	@-10~90℃		1	4	℃
	Active power			1.4		mW
F_CLK	Clock frequency				1000	kHz
	Power down current			1.5		µA

16.4.8 USB2.0 PHY Specification

16.4.8.1 Transmitter

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_IH	High input level	Classic (FS)	2.0			V
V_IL	Low input level	Classic (FS)			0.8	V
R_OUT	Output resistance	Classic mode (Vout= 0 or 3.3V)	40.5	45	49.5	Ω
R_OUT	Output resistance	HS mode (Vout = 0 to 800mV)	40.5	45	49.5	Ω
C_OUT	Output capacitance	Seen from D+ or D-		3.5	4.5	pF
V_M	Output common mode voltage	Classic (FS) mode	1.485	1.65	1.8	V
V_M	Output common mode voltage	HS mode	0.18	0.2	0.22	V
V_OH	Differential output signal high	Classic (FS); Io = 0mA	2.97	3.3	3.63	V
		Classic (FS); Io = 6mA	2.71	3.05	3.38	V
		HS mode; Io = 0mA	360	400	440	mV
V_OL	Differential output signal low	Classic (FS); Io = 0mA	0	-	0.3	V
		Classic (FS); Io = 6mA	-0.166	-0.155	-0.144	V
		HS mode; Io = 0mA	-10	0	10	mV

16.4.8.2 Receiver

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
R_CM	Receiver common mode	Classic mode	0.80	1.65	2.50	V
		HS mode (differential and squelch comparator)	0.10	0.125	0.20	V
		HS mode (disconnect comparator)	0.525	0.575	0.625	V

16.4.9 USB3.1 PHY Specification

16.4.9.1 Transmitter

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_TX-DIFF-PP	Differential_P-P TX voltage swing		0.8	1.0	1.2	V
V_{TX-DIFF-PP-LOW}	Low-power differential_P-P TX voltage swing		0.4	N/A	1.2	V
V_TX-DE-RATIO	TX de-emphasis		0.4	N/A	1.2	V
R_TX-DIFF-DC	DC differential impedance		72	N/A	120	Ω
V_{TX-RCV-DETECT}	The amount of voltage change allowed during receiver detection		N/A	N/A	0.6	V
C_AC-COUPLING	AC Coupling Capacitor		75	N/A	265	nF
V_{Tx-CM-IDLE-DELTA}	Transmitter idle common-mode voltage change		600	N/A	-600	mV
T_{CDR_SLEW_MAX}	Maximum slew-rate		N/A	N/A	10	ms/s

16.4.9.2 Receiver

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
R_RX-DC	Receiver DC common mode impedance		18	N/A	30	Ω
R_RX-DIFF-DC	DC differential impedance		72	N/A	120	Ω
V_{RX-LFPS-DET-DIFFp-p}	LFPS detect threshold		100	N/A	300	mV
C_{RX-AC-COUPLING}	AC coupling capacitor		297	N/A	363	nF
V_{RX-DIFF-PP-POST-EQ}	Differential RX peak-to-peak voltage		30	N/A	N/A	mV
C_RX-PARASITIC	RX input capacitance for return loss		N/A	N/A	1.1	pF
V_{RX- CM-DC-ACTIVEIDLE-} _{DELTA_P}	RX AC common mode voltage during the U1 to U0 transition		N/A	N/A	200	mV peak

16.4.10 MIPI CSI RX PHY Specification

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_IH	High input level	Classic (FS)	2.0	N/A	N/A	V
V_IL	Low input level	Classic (FS)	N/A	N/A	0.8	V
R_OUT	Output resistance	Classic mode (Vout = 0 or 3.3V)	40.5	45	49.5	Ω
R_OUT	Output resistance	HS mode (Vout = 0 to 800mV)	40.5	45	49.5	Ω
C_OUT	Output capacitance	Seen from D+ or D-	N/A	3.5	4.5	pF
V_M	Output common mode voltage	Classic (FS) mode	1.45	1.65	1.85	V
V_M	Output common mode voltage	HS mode	0.175	0.2	0.225	V
V_OH	Differential output signal high	Classic (FS); Io = 0mA	2.97	3.3	3.63	V
		Classic (FS); Io = 6mA	2.91	3	3.08	V
		HS mode; Io = 0mA	360	400	440	mV
V_OL	Differential output signal low	Classic (FS); Io = 0mA	-0.33	0	0.33	V
		Classic (FS); Io = 6mA	-0.42	-0.34	-0.31	V
		HS mode; Io = 0mA	-40	0	40	mV

16.4.11 MIPI TX PHY Specification

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_{DD18A_MIPITX}	1.8V analog supply voltage		1.62	1.8	1.98	V
F_REF	Input clock range			25		MHz
T_SKEW	Clock to data skew		-0.15		0.15	UI

16.4.11.1 MIPI CSI RX High-Speed Mode

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_CMRX(DC)	Common-mode voltage HS receive mode		70		330^1,2	mV
V_IDTH	Differential input high threshold				70³	mV
V_IDTH	Differential input high threshold				40⁴	mV
V_IDTL	Differential input low threshold		-70³			mV
V_IDTL	Differential input low threshold		-40⁴			mV
V_IHHS	Single-ended input high voltage				460¹	mV
V_ILHS	Single-ended input low voltage		-40¹			mV
F_CLK	Operating frequency		80		1250	MHz
V_TERM-EN	Single-ended threshold for HS termination enable				450	mV
Z_ID	Differential input impedance		80	100	125	Ω

Note:

Excluding possible additional RF interference of 100 mV peak sine wave beyond 450 MHz.
This table value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and variations below 450 MHz.
For devices supporting data rates <= 1.5Gbps
For devices supporting data rates > 1.5Gbps

16.4.11.2 MIPI CSI RX Low-Speed Mode

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
V_IH	Logic 1 input voltage		880¹			mV
V_IH	Logic 1 input voltage		740²			mV
V_IL	Logic 0 input voltage, not in ULP State				550	mV
V_IL-ULPS	Logic 0 input voltage, ULP State				300	mV
V_HYST	Input hysteresis		25			mV

Note:

Excluding possible additional RF interference of 100 mV peak sine wave beyond 450 MHz.
This table value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and variations below 450 MHz.

16.4.12 Driving-strength Table of GPIO

DS[3:0]	Source Current (mA)			Sink Current (mA)
DS[3:0]	Min.	Typ.	Max.	Min.	Typ.	Max.
0	0.8	1.1	1.5	0.7	1.1	1.6
1	1.1	1.6	2.2	1.1	1.7	2.3
2	2.3	3.3	4.3	2.1	3.3	4.7
3	3.4	4.9	6.5	3.2	5.0	7.0
4	4.5	6.6	8.6	4.2	6.6	9.3
5	5.7	8.2	10.8	5.3	8.3	11.7
6	6.8	9.9	13.0	6.3	9.9	13.9
7	7.9	11.5	15.1	7.4	11.6	16.2
8	9.0	13.1	17.2	8.4	13.2	18.5
9	10.2	14.8	19.4	9.4	14.8	20.8
10	11.3	16.4	21.6	10.5	16.5	23.1
11	12.4	18.1	23.7	11.5	18.1	25.4
12	13.5	19.6	25.8	12.6	19.7	27.6
13	14.7	21.3	28.0	13.6	21.4	29.9
14	15.8	22.9	30.1	14.6	23.0	32.1
15	16.9	24.6	32.3	15.7	24.6	34.4

16.4.13 Driving-strength Table of DVIO

DS[3:0]	Source Current (mA)			Sink Current (mA)
DS[3:0]	Min.	Typ.	Max.	Min.	Typ.	Max.
0	1.9	5.1	9.9	4.0	6.2	8.6
1	2.8	7.6	14.8	6.0	9.3	12.9
2	3.7	10.1	19.8	8.1	12.5	17.1
3	4.6	12.6	24.7	10.1	15.6	21.4
4	5.6	15.2	29.7	12.1	18.7	25.7
5	6.5	17.7	34.6	14.1	21.8	29.9
6	7.4	20.2	39.5	16.1	24.9	34.2
7	8.3	22.7	44.3	18.1	27.9	38.4
8	9.3	25.2	49.3	20.1	31.0	42.7
9	10.2	27.7	54.2	22.1	34.1	46.9
10	11.1	30.3	59.1	24.1	37.2	51.1
11	12.0	32.8	64.0	26.1	40.3	55.3
12	13.0	35.3	68.9	28.1	43.4	59.5
13	13.9	37.8	73.7	30.1	46.4	63.8
14	14.8	40.3	78.6	32.1	49.5	67.9
15	15.7	42.7	83.4	34.1	52.6	72.1

16.4.14 Resistance of Pull-up and down of GPIO

Parameters	Min.	Typ.	Max.	Unit	Remarks
R_SPU	1.6	2.1	3	kΩ	Resistance of strong pull up
R_PU	32	48	79	kΩ	Resistance of pull up
R_PD	30	44	65	kΩ	Resistance of pull down

16.4.15 Resistance of Pull-up and down of DVIO

Parameters	Min.	Typ.	Max.	Unit	Remarks
R_PU	29	35	45	kΩ	Resistance of pull up
R_PD	24	28	33	kΩ	Resistance of pull down

16.5 AC Characteristics

16.5.1 SPI-NAND AC Timing Specification

16.5.1.1 SPI-NAND Timing Diagram

...

16.5.1.2 SPI-NAND Timing Parameters (3.3V)

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
_tCK	Clock cycle for SPI flash		9.76	9.76		ns
_tCKH	Clock high-level width for SPI flash		4.88	4.88		ns
_tCKL	Clock low-level width for SPI flash		4.88	4.88		ns
_tSLCH	SPI_NAND_CEN active setup time relative to SPI_NAND_CLK		19.5			ns
_tDDLY	Write data output delay from SPI_CLK falling edge		0	0		ns
_tRDVLD	Read data valid time				8	ns

16.5.1.3 SPI-NAND Timing Parameters (1.8V)

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
_tCK	Clock cycle for SPI flash		6.5	7.5		ns
_tCKH	Clock high-level width for SPI flash		3.25	3.75		ns
_tCKL	Clock low-level width for SPI flash		3.25	3.75		ns
_tSLCH	SPI_NAND_CEN active setup time relative to SPI_NAND_CLK		13			ns
_tDDLY	Write data output delay from SPI_CLK Falling edge		0	0		ns
_tRDVLD	Read data valid time				8	ns

16.5.2 I2S Master AC Timing Specification

16.4.2.1 I2S Master Timing Diagram

...

16.5.2.2 I2S Master AC Timing Parameters

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_LR = 1/F_S	LRCK period (1/F_S)		5.208		31.25	µs
F_S	LRCK frequency		32		192	kHz
T_BCK = 1/ F_BCK	BCK period		81.38		488.28	ns
F_BCK	BCK frequency		2.048		12.288	MHz
T_BCKL	BCK pulse width low				244	ns
T_BCKH	BCK pulse width high				244	ns
T_LRB	LRCK edge to BCK rising edge		10			ns
T_DINS	I2S_DIN set-up time		10			ns
T_DINH	I2S_DIN hold time		10			ns
T_DOUTS	I2S_DOUT set-up time		10			ns
T_DOUTH	I2S_DOUT hold time		10			ns
T_smd	XCK to BCK active edge delay		0		15	ns
T_imd	XCK to LRCK delay		0		15	ns

Note: F_S (unit: Hz): 32K, 48K, 96K, 192K, 44.1K, 88.2K, 176.4K

16.5.3 I2S Slave AC Timing Specification

16.5.3.1 I2S Slave Timing Diagram

...

16.5.3.2 I2S Slave Timing Parameters

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
t_ds	DIN setup time before BCK rising edge			38.0		ns
t_dh	DIN hold time after BCK rising edge		30	44.0		ns
t_sckh	BCK high time			40		ns
t_sckl	BCK low time			40		ns
t_lrck	BCK falling edge to LRCK			2.8		ns

16.5.4 SPI NOR AC Timing Specification

16.5.4.1 SPI NOR Timing Diagram

...

16.5.4.1 NOR NAND Timing Parameters (3.3/1.8V)

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
_tCK	Clock cycle for SPI NOR Flash		9.76	9.76		ns
_tCKH	Clock high-level width for SPI NOR Flash		4.88	4.88		ns
_tCKL	Clock low-level width for SPI NOR Flash		4.88	4.88		ns
_tSLCH	SPI_NOR_CEN active setup time relative to SPI_NOR_CLK		19.5			ns
_tDDLY	Write data output delay from SPI_NOR_CLK falling edge		0	2.50		ns
_tRDVLD	Read data valid time				8	ns

16.5.5 SD/SDIO Timing Specification

16.5.5.1 SD/SDIO AC Timing Diagram

...

16.5.5.2 SD/SDIO (High-Speed) Timing Parameters

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
F_ck2	Clock frequency data transfer mode	High Speed	0		50	MHz
T_WL2	Clock low time	High Speed		12.1		ns
T_WH2	Clock high time	High Speed		9.0		ns
T_TLH2	Clock rise time	High Speed		1.5		ns
T_THL2	Clock fall time	High Speed		1.6		ns
T_SU2	Input set-up time	High Speed		14.7		ns
T_IH2	Input hold time	High Speed		4.3		ns
T_ODLY	Output delay time during data transfer mode	High Speed		9.3		ns
T_OH	Output hold time	High Speed		9.5		ns

Note: The default mode timing is covered by high speed mode.

16.5.5.3 SD/SDIO (SDR Mode) Timing Parameters

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
F_ck2	Clock frequency data transfer mode	SDR mode	0		200	MHz
	Clock duty	SDR mode	30	48	70	ns
T_TLH2	Clock rise time	SDR mode		0.8		ns
T_THL2	Clock fall time	SDR mode		0.65		ns
T_SU2	Input set-up time	SDR mode		0.78		ns
T_IH2	Input hold time	SDR mode		4.05		ns
T_ODLY	Output delay time during data transfer mode	SDR mode		3.18		ns
T_OH	Output hold time	SDR mode		3.775		ns

Note: The default mode timing is covered by high speed mode. SD/SDIO only focuses on duty cycle at 1.8V.

16.5.5.4 SD/SDIO (DDR Mode) Timing Diagram

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16.5.5.5 SD/SDIO (DDR mode) Timing Diagram

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
	Clock duty cycle	High Speed (DDR)	45	49.6	55	%
T_TLH	Clock rise time	High Speed (DDR)		0.84		ns
T_THL	Clock fall time	High Speed (DDR)		0.64		ns
T_ISU	Input set-up time (CMD, SDR)	High Speed (DDR)		14.76		ns
T_IH	Input hold time (CMD, SDR)	High Speed (DDR)		4.52		ns
T_ODLY	Output delay time during data transfer (CMD, SDR)	High Speed (DDR)		2.7		ns
T_oH	Output hold time (CMD, SDR)	High Speed (DDR)		2.2		ns
T_ISUddr	Input set-up time (DAT, DDR)	High Speed (DDR)		4.8		ns
T_IHddr	Input hold time (DAT, DDR)	High Speed (DDR)		4.24		ns
T_ODLYddr	Output delay time during data transfer (DAT, DDR)	High Speed (DDR)		7.6		ns

16.5.6 eMMC AC Timing Specification

16.5.6.1 eMMC Timing Diagram

...

16.5.6.2 eMMC (SDR Mode) Timing Parameters

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
F_CK2	Clock frequency data transfer mode	SDR mode	0		50	MHz
	Clock duty	SDR mode	30	50.5	70	ns
T_TLH2	Clock rise time	SDR mode		0.8		ns
T_THL2	Clock fall time	SDR mode		0.7		ns
T_SU2	Input set-up time	SDR mode		13.4		ns
T_IH2	Input hold time	SDR mode		5.5		ns
T_ODLY	Output delay time during data transfer mode	SDR mode		9.6		ns
T_OH	Output hold time	SDR mode		8.6		ns

Note: The default mode timing is covered by high speed mode.

16.5.6.3 eMMC (DDR mode) Timing Diagram

...

16.5.6.4 eMMC (DDR mode) Timing Parameters

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
	Clock duty cycle	High Speed (DDR)	45	50.7	55	%
T_WL	Clock low time	High Speed (DDR)		9.4		ns
T_WH	Clock High time	High Speed (DDR)		9.2		ns
T_TLH	Clock rise time	High Speed (DDR)		0.8		ns
T_THL	Clock fall time	High Speed (DDR)		0.7		ns
T_ISU	Input set-up time (CMD, SDR)	High Speed (DDR)		14.2		ns
T_IH	Input hold time (CMD, SDR)	High Speed (DDR)		4.2		ns
T_ODLY	Output delay time during data transfer (CMD, SDR)	High Speed (DDR)		9.1		ns
T_oH	Output hold time (CMD, SDR)	High Speed (DDR)		8.3		ns
t_RISE	Signal rise time (CMD, SDR)	High Speed (DDR)		0.8		ns
T_fall	Signal fall time (CMD, SDR)	High Speed (DDR)		0.8		ns
T_ISUddr	Input set-up time (DAT, DDR)	High Speed (DDR)		4.5		ns
T_IHddr	Input hold time (DAT, DDR)	High Speed (DDR)		4.5		ns
T_ODLYddr	Output delay time during Data Transfer (DAT, DDR)	High Speed (DDR)	4.5		5.8	ns
t_RISE	Signal rise time (DAT 0-7)	High Speed (DDR)		1.0		ns
t_FALL	Signal fall time (DAT 0-7)	High Speed (DDR)		0.9		ns

16.5.7 8-bit NAND AC Timing Specification

16.5.7.1 8-bit NAND (SDR Mode) Timing Diagram — 1

...

16.5.7.2 8-bit NAND (SDR Mode) Timing Parameters — 1

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_CS	CE# setup time	SDR mode	15	16.7		ns
T_CLS	CLE setup time	SDR mode	10	17.2		ns
T_CLH	CLE hold time	SDR mode	5	8.2		ns
T_ALS	ALE setup time	SDR mode	10	17.3		ns
T_ALH	ALE hold time	SDR mode	5	8		ns

16.5.7.3 8-bit NAND (SDR Mode) Timing Diagram — 2

...

16.5.7.4 8-bit NAND (SDR Mode) Timing Parameters — 2

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_DS	Data setup time	SDR mode	7	7.7		ns
T_DH	Data hold time	SDR mode	5	12.1		ns
T_WP	WE# pulse width	SDR mode	10	12.2		ns
T_WH	WE# high hold time	SDR mode	7	7.8		ns
T_WC	WE# cycle time	SDR mode	20	20		ns

16.5.7.5 8-bit NAND (SDR Mode) Timing Diagram — 3

...

16.5.7.6 8-bit NAND (SDR Mode) Timing Parameters — 3

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_RC	RE# cycle time	SDR mode	20	20.04		ns
T_RP	RE# pulse width	SDR mode	10	12.38		ns
T_REH	RE# high hold time	SDR mode	7	7.66		ns
T_REA	RE# access time	SDR mode		8.44	16	ns
T_RHOH	RE# high to output hold	SDR mode	15	16.32		ns
T_RLOH	RE# low to output hold	SDR mode	5	8.44		ns
T_RR	Ready to RE# low	SDR mode	20	86.07		ns

16.5.7.7 8-bit NAND (DDR Mode) Timing Diagram — 1

...

16.5.7.8 8-bit NAND (DDR Mode) Timing Parameters — 1

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_CH	CE# hold	DDR mode	3	5.30		ns
T_CAD	Command, address data delay	DDR mode	25	330		ns
T_CALH	ALE, CLE, W/R# hold	DDR mode	3	4.60		ns
T_CALS	ALE, CLE, W/R# setup	DDR mode	3	4.88		ns
T_CAH	DQ hold – command, address	DDR mode	3	4.87		ns
T_CK	Average CLK cycle time	DDR mode	15			ns
T_CKL	CLK cycle high	DDR mode	0.43		0.57	T_CK
T_CKH	CLK cycle low	DDR mode	0.43		0.57	T_CK

16.5.7.9 8-bit NAND (DDR mode) Timing Diagram — 2

...

16.5.7.10 8-bit NAND (DDR Mode) Timing Parameters — 2

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_DH	Data out hold	DDR mode	1.30	2.92		ns
T_DS	Data out setup	DDR mode	1.30	2.82		ns
T_DQSH	DQS output high pulse width	DDR mode	0.40	0.51	0.60	T_CK
T_DQSL	DQS output low pulse width	DDR mode	0.40	0.49	0.60	T_CK
T_DQSS	Data output	DDR mode	0.75	1.05	1.25	T_CK

16.5.7.11 8-bit NAND (DDR Mode) Timing Diagram — 3

...

16.5.7.12 8-bit NAND (DDR Mode) Timing Parameters — 3

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_AC	Access window of DQ[7:0] from CLK	DDR mode	3	12.53	20	ns
T_DQSCK	Access window of DQS from CLK	DDR mode		11.91	20	ns
T_DQSD	DQS, DQ[7:0] driven by NAND	DDR mode		9.76	18	ns
T_DQSQ	DQS-DQ skew	DDR mode		0.50	1.3	ns
T_WRCK	W/R# low to data output cycle	DDR mode	20	45.03		ns

16.5.8 SPI AC Timing Specification

16.5.8.1 SPI Timing Diagram

...

16.5.8.2 SPI MOSI Timing Parameters

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_LS1	Time from CSB (10%) to SCK (90%).			60.21		ns
T_LS2	Time from SCK (10%) to CSB 90%).			39.47		ns
T_CL	SCK low time.		20	19.90	81918	ns
T_CH	SCK high time.		20	20.11	81918	ns
T_SET	Time from changing MOSI (10%, 90%) to SCK (90%).		5	21.97		ns
T_HOL	Time from SCK (90%) to changing MOSI (10%, 90%).		15	18.32		ns
T_LH	Time between SPI cycles, CSB at high level (90%).		158			ns

16.5.8.3 SPI MISO Timing Parameters

Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
T_VAL1	Time from CSB (10%) to stable MISO (10%, 90%).		10	11.37		ns
T_VAL2	Time from SCK (10%) to stable MISO (10%, 90%).			12.32	15	ns

16.5.9 I2C AC Timing Specification

16.5.9.1 I2C Timing Diagram for Fast and Standard Mode

...

16.5.9.2 I2C Timing parameters for Fast and Standard Mode

Symbol	Parameters	Standard Mode	Fast Mode	Unit
		VDD = 1.8V
		MS = 1
		100kHz	400kHz
F_SCL	SCL clock frequency	99.41	396.8	kHz
T_LOW	Low period of the SCL clock	5.318	1.548	µs
T_HIGH	High period of the SCL clock	4.680	0.9117	µs
T_HD;STA	Hold time (repeated) START condition	4.718	0.9482	µs
T_SU;STA	Set-up time for a repeated START condition	5.390	1.020	µs
T_HD;DAT	Data hold time	2.016	0.00681	µs
T_SU;DAT	Data set-up time	3246.0	1454.0	ns
T_r	Rise time of both SDA and SCL signals	CLK = 54.50 DATA = 54.67	CLK = 56.00 DATA = 52.20	ns
T_f	Fall time of both SDA and SCL signals	CLK = 2.182 DATA = 2.628	CLK = 2.267 DATA = 2.328	ns
T_SU;STO	Set-up time for STOP condition	4.808	1.040	µs
T_VD;DAT	Data valid time	2.072	0.0092	µs
T_VD;ACK	Data valid acknowledge time	0.177	0.177	µs
T_BUF	Bus free time between a STOP and START condition	29.30	29.07	µs
T_SP	Pulse width of spikes that must be suppressed by the input filter			ns

16.5.9.3 I2C Timing Diagram for High-Speed mode

...

16.5.9.4 I2C Timing Parameters for High-speed Mode

Symbol	Parameters	High Speed Mode		Unit
		VDD = 1.8V	VDD = 3V
		MS = 1	MS = 0
		1.7MHz	1.7MHz
F_SCLH	SCLH clock frequency	1.251	1.266	MHz
T_LOW	Low period of the SCL clock	437.6	432.7	ns
T_HIGH	High period of the SCL clock	299.3	293.3	ns
T_HD;STA	Hold time (repeated) START condition	427.6	425.4	ns
T_SU;STA	Set-up time for a repeated START condition	511.7	504.2	ns
T_HD;DAT	Data hold time	28.03	24.37	ns
T_SU;DAT	Data set-up time	354.7	352.6	ns
T_rCL	Rise time of SCLH signal	55.33	53.33	ns
T_rCL1	Rise time of SCLH signal after a repeated START condition and after an acknowledge bit	55.83	54.92	ns
T_fCL	Fall time of SCLH signal	2.491	4.807	ns
T_rDA	Rise time of SDAH signal	53.00	52.00	ns
T_fDA	Fall time of SDAH signal	2.663	4.833	ns
T_SU;STO	Set-up time for STOP condition	493.3	479.4	ns

16.5.10 UART AC Timing Specification

16.5.10.1 UART Timing Diagram for TX

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16.5.10.2 UART Timing parameter for TX

16.5.10.2.1 UART0,1,2,3

...

16.5.10.2.2 UART6/7

...

16.5.10.3 UART Timing parameter for RX

...

16.5.10.3.1 UART0,1,2,3

...

16.5.10.3.2 UART6/7

...

16.5.11 RGMII AC Timing Specification

16.5.11.1 RGMII Timing Diagram for Internal-Delay Mode

...

16.5.11.2 RGMII Timing Parameters for Internal-Delay Mode

Symbol	Parameters	Min.	Typ.	Max.	Unit
	TXC & RXC frequency			125	MHz
T1	Clock cycle	7.20		8.80	ns
T2	TXD setup Time	1.20			ns
T3	TXD hold Time	1.20			ns
T4	RXD setup Time				ns
T5	RXD hold Time				ns

16.5.11.2 RGMII Timing Diagram for No-Internal-Delay Mode

...

16.5.11.3 RGMII Timing Parameters for No-Internal-Delay Mode

Symbol	Parameters	Min.	Typ.	Max.	Unit
	TXC & RXC frequency			125	MHz
T1	Clock cycle	7.20		8.80	ns
T2	Data to clock output skew	-500		+500	ps
T3	Data to clock input skew^[1]	-0.6		1.90	ns

Note: This implies that PC board design requires clocks to have no routing delay and the output skew from PHY could be ±500 ps.

16.5.12 RMII AC Timing Specification

16.5.12.1 RMII Timing Diagram

Image Added

16.5.12.2 RMII Timing Parameters

Symbol	Parameters	Min.	Typ.	Max.	Unit
T1	RMII clock period		20		ns
	RMII clock duty cycle	35		65	%
T2	TX_Data, TX_EN setup to RMII clock rising	4			ns
T3	TX_Data, TX_EN hold from RMII clock rising	2			ns
T4	RXD, CRSDV setup time	2			ns
T5	RXD, CRSDV hold time	2			ns

16.6 Power Consumption

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

I₀₈

I_1.1

I_1.8

I_3.0

I_3.3

0.8V supply current

1.1V supply current

1.8V supply current

3.0V supply current

3.3V supply current

Chip leakage is 182 mA @0.8V

including:

CA55 @1.8GHz,

NPU @900MHz with 0.85V

2675

280

42.5

65.5

199.5

4243

285

44.7

67

213.5

mA

Power Dissipation

3.38

4.69

W

Note: The power consumption is based on a chip with leakage current equals to 182 mA.

Note: The NPU and CA55 power is based on 0.85V.

Note: The test condition is defined by Vendor.

Note: The T_J is -30℃ to 125℃

17. Ball Map

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18. Ball Definition

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Page Comparison

Versions Compared

Old Version 77

New Version 78

Key

16 Electric Characteristics

16.

1 Absolute Maximum Ratings

16.2 Driving-strength Table of DVIO

16.3 Resistance of Pull-up and down of GPIO

16.4 Resistance of Pull-up and down of DVIO

16.2 Thermal Information

16.3 ESD Ratings

16.4 DC Characteristics

16.4.1 3.0/1.8V DVIO Specification (3.0V Mode)

16.4.2 3.0/1.8V DVIO Specification (1.8V Mode)

16.4.3 1.8V GPIO Specification

16.4.4 Crystal XIN 25MHz Specification

16.4.5 Crystal XIN 32.678kHzSpecification

16.4.6 SAR ADC Specification

16.4.7 Thermal Sensor Specification

16.4.8 USB2.0 PHY Specification

16.4.8.1 Transmitter

16.4.8.2 Receiver

16.4.9 USB3.1 PHY Specification

16.4.9.1 Transmitter

16.4.9.2 Receiver

16.4.10 MIPI CSI RX PHY Specification

16.4.11 MIPI TX PHY Specification

16.4.11.1 MIPI CSI RX High-Speed Mode

16.4.11.2 MIPI CSI RX Low-Speed Mode

16.4.12 Driving-strength Table of GPIO

16.4.13 Driving-strength Table of DVIO

16.4.14 Resistance of Pull-up and down of GPIO

16.4.15 Resistance of Pull-up and down of DVIO

16.5 AC Characteristics

16.5.1 SPI-NAND AC Timing Specification

16.5.1.1 SPI-NAND Timing Diagram

16.5.1.2 SPI-NAND Timing Parameters (3.3V)

16.5.1.3 SPI-NAND Timing Parameters (1.8V)

16.5.2 I2S Master AC Timing Specification

16.4.2.1 I2S Master Timing Diagram

16.5.2.2 I2S Master AC Timing Parameters

16.5.3 I2S Slave AC Timing Specification

16.5.3.1 I2S Slave Timing Diagram

16.5.3.2 I2S Slave Timing Parameters

16.5.4 SPI NOR AC Timing Specification

16.5.4.1 SPI NOR Timing Diagram

16.5.4.1 NOR NAND Timing Parameters (3.3/1.8V)

16.5.5 SD/SDIO Timing Specification

16.5.5.1 SD/SDIO AC Timing Diagram

16.5.5.2 SD/SDIO (High-Speed) Timing Parameters

16.5.5.3 SD/SDIO (SDR Mode) Timing Parameters

16.5.5.4 SD/SDIO (DDR Mode) Timing Diagram

16.5.5.5 SD/SDIO (DDR mode) Timing Diagram

16.5.6 eMMC AC Timing Specification

16.5.6.1 eMMC Timing Diagram

16.5.6.2 eMMC (SDR Mode) Timing Parameters

16.5.6.3 eMMC (DDR mode) Timing Diagram

16.5.6.4 eMMC (DDR mode) Timing Parameters

16.5.7 8-bit NAND AC Timing Specification

16.5.7.1 8-bit NAND (SDR Mode) Timing Diagram — 1

16.5.7.2 8-bit NAND (SDR Mode) Timing Parameters — 1

16.5.7.3 8-bit NAND (SDR Mode) Timing Diagram — 2

16.5.7.4 8-bit NAND (SDR Mode) Timing Parameters — 2

16.5.7.5 8-bit NAND (SDR Mode) Timing Diagram — 3

16.5.7.6 8-bit NAND (SDR Mode) Timing Parameters — 3

16.5.7.7 8-bit NAND (DDR Mode) Timing Diagram — 1

16.5.7.8 8-bit NAND (DDR Mode) Timing Parameters — 1

16.5.7.9 8-bit NAND (DDR mode) Timing Diagram — 2

16.5.7.10 8-bit NAND (DDR Mode) Timing Parameters — 2

16.5.7.11 8-bit NAND (DDR Mode) Timing Diagram — 3

16.5.7.12 8-bit NAND (DDR Mode) Timing Parameters — 3

16.5.8 SPI AC Timing Specification

16.5.8.1 SPI Timing Diagram

16.5.8.2 SPI MOSI Timing Parameters

16.5.8.3 SPI MISO Timing Parameters

16.5.9 I2C AC Timing Specification

16.5.9.1 I2C Timing Diagram for Fast and Standard Mode

16.5.9.2 I2C Timing parameters for Fast and Standard Mode

16.4.4 Crystal X_IN 25MHz Specification

16.4.5 Crystal X_IN 32.678kHzSpecification