Page Comparison

RX0

2

2

Not available in this package

RX1

2

2

Not available in this package

RX2

2

2

RX3

2

2

Not available for version A chips.

RX4

2

2

RX5

4

4

Ball Name

ST

DS[3:0]

PU

PD

Remarks

G_MX20

1

3

1

0

Pull-up

G_MX21

1

3

1

0

Pull-up

G_MX22

1

3

0

1

Pull-down

G_MX23

1

3

1

0

Pull-up

G_MX24

1

3

1

0

Pull-up

G_MX25

1

3

1

0

Pull-up

G_MX26

1

3

1

0

Pull-up

G_MX27

1

3

0

1

Pull-down

G_MX28

1

3

1

0

Pull-up

G_MX29

1

3

1

0

Pull-up

G_MX30

1

3

1

0

Pull-up

G_MX31

1

3

1

0

Pull-up

G_MX32

1

3

0

1

Pull-down

G_MX33

1

3

1

0

Pull-up

G_MX34

1

3

1

0

Pull-up

G_MX35

1

3

1

0

Pull-up

G_MX36

1

3

1

0

Pull-up

G_MX37

1

3

1

0

Pull-up

G_MX38

1

3

0

0

HiZHi-Z

G_MX39

1

3

0

0

HiZHi--Z

G_MX40

1

3

0

0

HiZHi-Z

G_MX41

1

3

0

0

HiZHi-Z

G_MX42

1

3

0

0

HiZHi-Z

G_MX43

1

3

0

0

HiZHi-Z

G_MX44

1

3

0

0

HiZHi-Z

G_MX45

1

3

0

0

HiZHi-Z

G_MX46

1

3

0

0

HiZHi-Z

G_MX47

1

3

0

0

HiZHi-Z

G_MX48

1

3

0

0

HiZHi-Z

G_MX49

1

3

0

0

HiZHi-Z

AO_MX0

1

3

1

0

Pull-up

AO_MX1

1

3

1

0

Pull-up

AO_MX2

1

3

1

0

Pull-up

AO_MX3

1

3

1

0

Pull-up

AO_MX4

1

3

1

0

Pull-up

AO_MX5

1

3

1

0

Pull-up

AO_MX6

1

3

1

0

Pull-up

AO_MX7

1

3

1

0

Pull-up

AO_MX8

1

3

1

0

Pull-up

AO_MX9

1

3

1

0

Pull-up

AO_MX10

1

3

1

0

Pull-up

AO_MX11

1

3

1

0

Pull-up

AO_MX12

1

3

1

0

Pull-up

AO_MX13

1

3

1

0

Pull-up

AO_MX14

1

3

1

0

Pull-up

AO_MX15

1

3

1

0

Pull-up

AO_MX16

1

3

1

0

Pull-up

AO_MX17

1

3

0

1

Pull-down

AO_MX18

1

3

0

1

Pull-down

AO_MX19

1

3

1

0

Pull-up

AO_MX20

1

3

0

1

Pull-down

AO_MX21

1

3

1

0

Pull-up

AO_MX22

1

3

0

1

Pull-down

AO_MX23

1

3

0

1

Pull-down

AO_MX24

1

3

0

1

Pull-down

AO_MX25

1

3

0

1

Pull-down

AO_MX26

1

3

0

1

Pull-down

AO_MX27

1

3

1

0

Pull-up

AO_MX28

1

3

0

1

Pull-down

AO_MX29

1

3

1

0

Pull-up

Symbol

Parameter

Min.

Max.

Unit

V_DD33

Supply voltage 3.3V

-0.3.0

3.63

V

V_{DD_CA55}

Supply voltage 0.85V for CA55

-0.830

1.8905

V

V_{DD_NPU}

Supply voltage 0.85V for NPU

-0.83

0.89

V

V_DD08

Supply voltage 0.8V for DRAM, video codec, chip top system, CM4 (AO (Always On) and RTC power domain, and other 0.8V for Analog analog core power

-0.723

0.88

V

V_DD18

Supply voltage 1.8V

1-0.723

1.98

V

V_DD11

Supply voltage 1.1V

1-0.063

1.17

V

V_DD30

Supply voltage 3.0V²

2-0.73

3.346

V

V_O33

Output voltage 3.3V

-0.3.0

3.63

V

V_O18

Output voltage 1.8V

1-0.723

1.98

V

V_I33

3.3V input voltage (3.3V tolerant inputs)

-0.3.0

3.63

V

V_I18

1.8V input voltage

1-0.723

1.98

V

T_J

Junction temperature

-30

120

°C

T_STG

Storage temperature

-40

150

°C

Symbol

Parameters

Min.

Max.

Unit

V_ESD

Human Body Model (test Per per JS-001-2017)

-2

+2

kV

Charge Device Mode (test Per per JESD22-C101F)

-500

+500

V

I_LA

Latch-up tolerance (test Per per JESD78E)

-100

+100

mA

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

V_IH

High-level input voltage

-

1.875

-

3.3

V

V_IL

Low-level input voltage

-

0

-

0.75

V

V_OH

High-level output voltage

2.75

-

V_DD33

V

V_OL

Low-level output voltage

0

-

0.375

V

I_OZ

High-impedance state output current

V_O = 0 to V_DD30

±1³

mA

C_I

Input capacitance

5

pF

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

Power for SAR ADC

1.62

1.80

1.98

V

RS_SAR

Resolution

12

bits

ENOB

Effective number of bits

10

bits

INL_SAR

Integral nonlinearity

non-linearity

F_IN = 10 Hz

F_S = 250 kHz

3

LSB

DNL_SAR

Differential nonlinearitynon-linearity

3

LSB

Input range

0

V_DD18

V

Power down current

4.52

46.8

µA

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

V_TX-DIFF-PP

Differential TX_P-P TX voltage swing

0.8

1.0

1.2

V

V_{TX-DIFF-PP-LOW}

Low-power differential
TX_P-P
TX voltage swing

0.4

N/A

1.2

V

V_TX-DE-RATIO

TX de-emphasis

0.4

N/A

1.2

V

R_TX-DIFF-DC

DC differential impedance

72

N/A

120

Ω

V_{TX-RCV-DETECT}

The amount of voltage change allowed during receiver detection

N/A

N/A

0.6

V

C_AC-COUPLING

AC Coupling Capacitor

75

N/A

265

nF

V_{Tx-CM-IDLE-DELTA}

Transmitter idle common-mode voltage change

600

N/A

-600

mV

T_{CDR_SLEW_MAX}

Maximum slew-rate

N/A

N/A

10

msmS/sS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

V_IH

High input level

Classic (FS)

2.0N/A

N/A

V

V_IL

Low input level

Classic (FS)

N/A

0.8

V

R_OUT

Output resistance

Classic mode

(Vout = 0 or 3.3V)

40.5

45

49.5

Ω

HS mode

(Vout = 0 to 800mV)

40.5

45

49.5

Ω

C_OUT

Output capacitance

Seen from D+ or D-

3.5

4.5

pF

V_M

Output common mode voltage

Classic (FS) mode

1.45

1.65

1.85

V

HS mode

0.175

0.2

0.225

V

V_OH

Differential output signal high

Classic (FS);

Io = 0mA

2.97

3.3

3.63

V

Classic (FS);

Io = 6mA

2.91

3

3.08

V

HS mode; Io = 0mA

360

400

440

mV

V_OL

Differential output signal low

Classic (FS);

Io = 0mA

-0.33

0

0.33

V

Classic (FS);

Io = 6mA

-0.42

-0.34

-0.31

V

HS mode; Io = 0mA

-40

0

40

mV

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

_tCK

Clock cycle for SPI flash

9.76

9.76

nsnS

_tCKH

Clock high-level width for SPI flash

4.88

4.88

nsnS

_tCKL

Clock low-level width for SPI flash

4.88

4.88

nsnS

_tSLCH

SPI_NAND_CEN active setup time relative to SPI_NAND_CLK

19.5

nsnS

_tDDLY

Write data output delay from SPI_CLK falling edge

0

0

nsnS

_tRDVLD

Read data valid time

8

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

_tCK

Clock cycle for SPI flash

6.5

7.5

nsnS

_tCKH

Clock high-level width for SPI flash

3.25

3.75

nsnS

_tCKL

Clock low-level width for SPI flash

3.25

3.75

nsnS

_tSLCH

SPI_NAND_CEN active setup time relative to SPI_NAND_CLK

13

nsnS

_tDDLY

Write data output delay from SPI_CLK Falling edge

0

0

nsnS

_tRDVLD

Read data valid time

8

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

t_ds

DIN setup time before BCK rising edge

38.0

nsnS

t_dh

DIN hold time after BCK rising edge

30

44.0

nsnS

t_sckh

BCK high time

40

nsnS

t_sckl

BCK low time

40

nsnS

t_lrck

BCK falling edge to LRCK

2.8

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

_tCK

Clock cycle for SPI NOR Flash

9.76

9.76

nsnS

_tCKH

Clock high-level width for SPI NOR Flash

4.88

4.88

nsnS

_tCKL

Clock low-level width for SPI NOR Flash

4.88

4.88

nsnS

_tSLCH

SPI_NOR_CEN active setup time relative to SPI_NOR_CLK

19.5

nsnS

_tDDLY

Write data output delay from SPI_NOR_CLK falling edge

0

2.50

nsnS

_tRDVLD

Read data valid time

8

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

F_ck2

Clock frequency data transfer mode

High Speed

0

50

MHz

T_WL2

Clock low time

High Speed

12.1

nsnS

T_WH2

Clock high time

High Speed

9.0

nsnS

T_TLH2

Clock rise time

High Speed

1.5

nsnS

T_THL2

Clock fall time

High Speed

1.6

nsnS

T_SU2

Input set-up time

High Speed

14.7

nsnS

T_IH2

Input hold time

High Speed

4.3

nsnS

T_ODLY

Output delay time during data transfer mode

High Speed

9.3

nsnS

T_OH

Output hold time

High Speed

9.5

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

F_ck2

Clock frequency data transfer mode

SDR mode

0

200

MHz

Clock duty

SDR mode

30

48

70

nsnS

T_TLH2

Clock rise time

SDR mode

0.8

nsnS

T_THL2

Clock fall time

SDR mode

0.65

nsnS

T_SU2

Input set-up time

SDR mode

0.78

nsnS

T_IH2

Input hold time

SDR mode

4.05

nsnS

T_ODLY

Output delay time during data transfer mode

SDR mode

3.18

nsnS

T_OH

Output hold time

SDR mode

3.775

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

Clock duty cycle

High Speed (DDR)

45

49.6

55

%

T_TLH

Clock rise time

High Speed (DDR)

0.84

nsnS

T_THL

Clock fall time

High Speed (DDR)

0.64

nsnS

T_ISU

Input set-up time (CMD, SDR)

High Speed (DDR)

14.76

nsnS

T_IH

Input hold time (CMD, SDR)

High Speed (DDR)

4.52

nsnS

T_ODLY

Output delay time during data transfer (CMD, SDR)

High Speed (DDR)

2.7

nsnS

T_oH

Output hold time (CMD, SDR)

High Speed (DDR)

2.2

nsnS

T_ISUddr

Input set-up time (DAT, DDR)

High Speed (DDR)

4.8

nsnS

T_IHddr

Input hold time (DAT, DDR)

High Speed (DDR)

4.24

nsnS

T_ODLYddr

Output delay time during data transfer (DAT, DDR)

High Speed (DDR)

7.6

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

F_CK2

Clock frequency data transfer mode

SDR mode

0

50

MHz

Clock duty

SDR mode

30

50.5

70

nsnS

T_TLH2

Clock rise time

SDR mode

0.8

nsnS

T_THL2

Clock fall time

SDR mode

0.7

nsnS

T_SU2

Input set-up time

SDR mode

13.4

nsnS

T_IH2

Input hold time

SDR mode

5.5

nsnS

T_ODLY

Output delay time during data transfer mode

SDR mode

9.6

nsnS

T_OH

Output hold time

SDR mode

8.6

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

Clock duty cycle

High Speed (DDR)

45

50.7

55

%

T_WL

Clock low time

High Speed (DDR)

9.4

nsnS

T_WH

Clock High time

High Speed (DDR)

9.2

nsnS

T_TLH

Clock rise time

High Speed (DDR)

0.8

nsnS

T_THL

Clock fall time

High Speed (DDR)

0.7

nsnS

T_ISU

Input set-up time (CMD, SDR)

High Speed (DDR)

14.2

nsnS

T_IH

Input hold time (CMD, SDR)

High Speed (DDR)

4.2

nsnS

T_ODLY

Output delay time during data transfer (CMD, SDR)

High Speed (DDR)

9.1

nsnS

T_oH

Output hold time (CMD, SDR)

High Speed (DDR)

8.3

nsnS

t_RISE

Signal rise time (CMD, SDR)

High Speed (DDR)

0.8

nsnS

T_fall

Signal fall time (CMD, SDR)

High Speed (DDR)

0.8

nsnS

T_ISUddr

Input set-up time (DAT, DDR)

High Speed (DDR)

4.5

nsnS

T_IHddr

Input hold time (DAT, DDR)

High Speed (DDR)

4.5

nsnS

T_ODLYddr

Output delay time during Data Transfer (DAT, DDR)

High Speed (DDR)

4.5

5.8

nsnS

t_RISE

Signal rise time (DAT 0-7)

High Speed (DDR)

1.0

nsnS

t_FALL

Signal fall time (DAT 0-7)

High Speed (DDR)

0.9

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

T_CS

CE# setup time

SDR mode

15

16.7

nsnS

T_CLS

CLE setup time

SDR mode

10

17.2

nsnS

T_CLH

CLE hold time

SDR mode

5

8.2

nsnS

T_ALS

ALE setup time

SDR mode

10

17.3

nsnS

T_ALH

ALE hold time

SDR mode

5

8

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

T_DS

Data setup time

SDR mode

7

7.7

nsnS

T_DH

Data hold time

SDR mode

5

12.1

nsnS

T_WP

WE# pulse width

SDR mode

10

12.2

nsnS

T_WH

WE# high hold time

SDR mode

7

7.8

nsnS

T_WC

WE# cycle time

SDR mode

20

20

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

T_RC

RE# cycle time

SDR mode

20

20.04

nsnS

T_RP

RE# pulse width

SDR mode

10

12.38

nsnS

T_REH

RE# high hold time

SDR mode

7

7.66

nsnS

T_REA

RE# access time

SDR mode

8.44

16

nsnS

T_RHOH

RE# high to output hold

SDR mode

15

16.32

nsnS

T_RLOH

RE# low to output hold

SDR mode

5

8.44

nsnS

T_RR

Ready to RE# low

SDR mode

20

86.07

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

T_CH

CE# hold

DDR mode

3

5.30

nsnS

T_CAD

Command, address data delay

DDR mode

25

330

nsnS

T_CALH

ALE, CLE, W/R# hold

DDR mode

3

4.60

nsnS

T_CALS

ALE, CLE, W/R# setup

DDR mode

3

4.88

nsnS

T_CAH

DQ hold – command, address

DDR mode

3

4.87

nsnS

T_CK

Average CLK cycle time

DDR mode

15

nsnS

T_CKL

CLK cycle high

DDR mode

0.43

0.57

T_CK

T_CKH

CLK cycle low

DDR mode

0.43

0.57

T_CK

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

T_DH

Data out hold

DDR mode

1.30

2.92

nsnS

T_DS

Data out setup

DDR mode

1.30

2.82

nsnS

T_DQSH

DQS output high pulse width

DDR mode

0.40

0.51

0.60

T_CK

T_DQSL

DQS output low pulse width

DDR mode

0.40

0.49

0.60

T_CK

T_DQSS

Data output

DDR mode

0.75

1.05

1.25

T_CK

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

T_AC

Access window of DQ[7:0] from CLK

DDR mode

3

12.53

20

nsnS

T_DQSCK

Access window of DQS from CLK

DDR mode

11.91

20

nsnS

T_DQSD

DQS, DQ[7:0] driven by NAND

DDR mode

9.76

18

nsnS

T_DQSQ

DQS-DQ skew

DDR mode

0.50

1.3

nsnS

T_WRCK

W/R# low to data output cycle

DDR mode

20

45.03

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

T_LS1

Time from CSB (10%) to SCK (90%).

60.21

nsnS

T_LS2

Time from SCK (10%) to CSB 90%).

39.47

nsnS

T_CL

SCK low time.

20

19.90

81918

nsnS

T_CH

SCK high time.

20

20.11

81918

nsnS

T_SET

Time from changing MOSI (10%, 90%) to SCK (90%).

5

21.97

nsnS

T_HOL

Time from SCK (90%) to changing MOSI (10%, 90%).

15

18.32

nsnS

T_LH

Time between SPI cycles, CSB at high level (90%).

158

nsnS

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Unit

T_VAL1

Time from CSB (10%) to stable MISO (10%, 90%).

10

11.37

nsnS

T_VAL2

Time from SCK (10%) to stable MISO (10%, 90%).

12.32

15

nsnS

Symbol

Parameters

Standard Mode

Fast Mode

Unit

VDD = 1.8V

MS = 1

100kHz

400kHz

F_SCL

SCL clock frequency

99.41

396.8

kHz

T_LOW

Low period of the SCL clock

5.318

1.548

µsµS

T_HIGH

High period of the SCL clock

4.680

0.9117

µsµS

T_HD;STA

Hold time (repeated) START condition

4.718

0.9482

µsµS

T_SU;STA

Set-up time for a repeated START condition

5.390

1.020

µsµS

T_HD;DAT

Data hold time

2.016

0.00681

µsµS

T_SU;DAT

Data set-up time

3246.0

1454.0

nsnS

T_r

Rise time of both SDA and SCL signals

CLK = 54.50

DATA = 54.67

CLK = 56.00

DATA = 52.20

nsnS

T_f

Fall time of both SDA and SCL signals

CLK = 2.182

DATA = 2.628

CLK = 2.267

DATA = 2.328

nsnS

T_SU;STO

Set-up time for STOP condition

4.808

1.040

µsµS

T_VD;DAT

Data valid time

2.072

0.0092

µsµS

T_VD;ACK

Data valid acknowledge time

0.177

0.177

µsµS

T_BUF

Bus free time between a STOP and START condition

29.30

29.07

µsµS

T_SP

Pulse width of spikes that must be suppressed by the input filter

nsnS

Symbol

Parameters

High Speed Mode

Unit

VDD = 1.8V

VDD = 3V

MS = 1

MS = 0

1.7MHz

1.7MHz

F_SCLH

SCLH clock frequency

1.251

1.266

MHz

T_LOW

Low period of the SCL clock

437.6

432.7

nsnS

T_HIGH

High period of the SCL clock

299.3

293.3

nsnS

T_HD;STA

Hold time (repeated) START condition

427.6

425.4

nsnS

T_SU;STA

Set-up time for a repeated START condition

511.7

504.2

nsnS

T_HD;DAT

Data hold time

28.03

24.37

nsnS

T_SU;DAT

Data set-up time

354.7

352.6

nsnS

T_rCL

Rise time of SCLH signal

55.33

53.33

nsnS

T_rCL1

Rise time of SCLH signal after a repeated START condition and after an acknowledge bit

55.83

54.92

nsnS

T_fCL

Fall time of SCLH signal

2.491

4.807

nsnS

T_rDA

Rise time of SDAH signal

53.00

52.00

nsnS

T_fDA

Fall time of SDAH signal

2.663

4.833

nsnS

T_SU;STO

Set-up time for STOP condition

493.3

479.4

nsnS

AO

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

1.8V

T_txd

TXCLK high pulse

BR=115200

8.192

8.681

9.06

µsµS

T_txd

TXCLK high pulse

BR=921600

1.025

1.085

1.173

µsµS

T_txd

TXCLK high pulse

BR=3000000

0.315

0.331

0.347

µsµS

3V

T_txd

TXCLK high pulse

BR=115200

8.192

8.680

9.060

µsµS

T_txd

TXCLK high pulse

BR=921600

1.025

1.085

1.173

µsµS

T_txd

TXCLK high pulse

BR=3000000

0.315

0.331

0.347

µsµS

AO

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

1.8V

T_rxd

RXCLK high pulse

BR=115200

8.192

8.680

9.06

µsµS

T_rxd

RXCLK high pulse

BR=921600

1.025

1.085

1.173

µsµS

T_rxd

RXCLK high pulse

BR=3000000

0.315

0.331

0.347

µsµS

3V

T_rxd

RXCLK high pulse

BR=115200

8.192

8.680

9.06

µsµS

T_rxd

RXCLK high pulse

BR=921600

1.025

1.085

1.173

µsµS

T_rxd

RXCLK high pulse

BR=3000000

0.315

0.331

0.347

µsµS

Symbol

Parameters

Min.

Typ.

Max.

Unit

TXC & RXC frequency

125

MHz

T1

Clock cycle

7.20

8.80

nsnS

T2

TXD setup Time

1.20

nsnS

T3

TXD hold Time

1.20

nsnS

T4

RXD setup Time

nsnS

T5

RXD hold Time

nsnS

Symbol

Parameters

Min.

Typ.

Max.

Unit

TXC & RXC frequency

125

MHz

T1t1

Clock cycle

7.20

8.80

nsnS

T2t2

Data to clock output skew

-5000.5

+5000.5

psnS

T3t3

Data to clock input skew^[1]

-0.6

+1.90

nsnS

Symbol

Parameters

Min.

Typ.

Max.

Unit

T1t1

RMII clock period

20

nsnS

RMII clock duty cycle

35

65

%

T2t2

TX_Data, TX_EN setup to RMII clock rising

4

nsnS

T3t3

TX_Data, TX_EN hold from RMII clock rising

2

nsnS

T4t4

RXD, CRSDV setup time

2

nsnS

T5t5

RXD, CRSDV hold time

2

nsnS

Ball No.

Ball Name

Function Type

A2

BP_A[30]

DRAM address and command

A4

BP_A[27]

DRAM address and command

A6

BP_A[25]

DRAM address and command

A8

BP_A[21]

DRAM address and command

A10

BP_A[17]

DRAM address and command

A12

BP_A[4]

DRAM address and command

A14

BP_A[15]

DRAM address and command

A16

BP_A[12]

DRAM address and command

A18

BP_A[9]

DRAM address and command

A20

BP_A[6]

DRAM address and command

A22

BP_D[14]

DRAM data and strobe

A23

BP_D[13]

DRAM data and strobe

A25

BP_D[22]

DRAM data and strobe

A27

BP_D[20]

DRAM data and strobe

A29

BP_D[17]

DRAM data and strobe

A31

AO_MX28

GPIO, PWM0, UA2 in AO domain

A33

AO_MX25

GPIO, SPI4, SPI5 in AO domain

A35

AO_MX23

GPIO, SPI4, SPI5 in AO domain

B1

BP_A[33]

DRAM address and command

B2

BP_A[31]

DRAM address and command

B3

BP_A[29]

DRAM address and command

B4

BP_A[28]

DRAM address and command

B5

BP_A[26]

DRAM address and command

B6

GND

GND

B7

BP_A[24]

DRAM address and command

B8

GND

GND

B9

BP_A[20]

DRAM address and command

B10

GND

GND

B11

BP_A[16]

DRAM address and command

B12

GND

GND

B13

BP_A[5]

DRAM address and command

B14

GND

GND

B15

BP_A[14]

DRAM address and command

B16

BP_A[13]

DRAM address and command

B17

BP_A[11]

DRAM address and command

B18

BP_A[10]

DRAM address and command

B19

BP_A[8]

DRAM address and command

B20

BP_A[7]

DRAM address and command

B21

GND

GND

B22

BP_D[15]

DRAM data and strobe

B23

BP_D[12]

DRAM data and strobe

B24

GND

GND

B25

BP_D[21]

DRAM data and strobe

B26

GND

GND

B27

BP_D[19]

DRAM data and strobe

B28

BP_D[18]

DRAM data and strobe

B29

BP_D[16]

DRAM data and strobe

B30

GND

GND

B31

AO_MX29

GPIO, PWM1 or UA2 in AO domain

B32

AO_MX26

GPIO, I2C2 or UA2 in AO domain

B33

AO_MX27

GPIO, I2C2 or UA2 in AO domain

B34

AO_MX24

GPIO, SPI4 or SPI5 in AO domain

B35

AO_MX22

GPIO, SPI4 or SPI5 in AO domain

B36

AO_MX20

GPIO or I2C1 in AO domain

B37

AO_MX21

GPIO or I2C1 in AO domain

C2

BP_A[32]

DRAM address and command

C36

AO_MX18

GPIO, I2C0 or UA0 in AO domain

D1

BP_A[35]

DRAM address and command

D2

BP_A[34]

DRAM address and command

D36

AO_MX17

GPIO, SPI0 or UA1 in AO domain

D37

AO_MX16

GPIO, SPI0 or UA1 in AO domain

E2

GND

GND

E36

AO_MX15

GPIO, SPI0 or UA1 in AO domain

F1

BP_D[38]

DRAM data and strobe

F2

BP_D[39]

DRAM data and strobe

F36

AO_MX13

GPIO or UA3 in AO domain

F37

AO_MX12

GPIO or UA3 in AO domain

G2

BP_D[37]

DRAM data and strobe

G36

AO_MX11