This document elucidates the application circuitry circuits associated with the SP7350. It serves as a supplementary resource to the specification of the SP7350.
...
All power sources should be managed using the CM4_PWR_EN signal. Specifically, when CM4_PWR_EN is set to LOW, all power supplies, including those for the CM4 and Main power domain, should be deactivated.
Please refer to the provided power scheme for details on power control.
...
Refer to the power scheme illustrated below. All powers in the main power domain should be controlled by both CM4_PWR_EN and MAIN_PWR_EN signals. Specifically, all powers in the main power domain are only turned on when both CM4_PWR_EN and MAIN_PWR_EN are set to HIGH.
It's important to note that during cold booting, CM4_PWR_EN goest to HIGH to initiate the booting process. Therefore, the default state ofMAIN_PWR_EN (when the GPIO is not yet programmed) should be HIGH to allow the CA55 to start booting.
...
Typically, MAIN_PWR_EN is controlled by a GPIO in the CM4 domain. CM4 can directly set the power of the main power domain to either on or off.
...
DDR Type | Max. Clock | Max. Data Rate | Max. BW (1 ch) | Max. BW (2 ch) |
|---|---|---|---|---|
LPDDR4 | 1.600 GHz | 3200 MT/s | 6.4 GB/s | 12.8 GB/s |
DDR4 | 1.333 GHz | 2666 MT/s | 5.3 GB/s | 10.7 GB/s |
LPDDR3 / DDR3 / DDR3L | 0.933 MHz | 1866 MT/s | 3.7 GB/s | 7.5 GB/s |
Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.
5.1 Data Bus and Data Strobe Signals Wiring
...
ILIM = 6800/6800 = 1.0 (A)
...
Note that R218 and C247 are requested and defined by OTG specification. Do not alter their values.
The UPHY0_DRV5V_EN signal controls VBUS on/off states, generated by the OTG hardware of SP7350.
...
17.2 MIPI-RX2 and MIPI-RX3
Note that MIPI-RX2 is not available for version A chips.
When CPIO is disabled, MIPI-RX2 and MIPI-RX3 are available for use. MIPI-RX2 supports four data and one clock lanes (4d1c) with 4 virtual channels if MIPI-RX3 is not enabled. However, if MIPI-RX3 is enabled, both MIPI-RX2 and RX3 support two data and one clock lanes (2d1c). Each data lane can transmit up to 1.5 Gbps. Please refer to the table for pin sharing between MIPI-RX2, MIPI-RX3, and CPIO.
...
Below is the pin-out for channel 0 of the SP7350 audio I2S interface:
Signal Name | Pins of X1 Position | Pins of X2 Position | Type | Config Bits | Remarks | |||||||||
AU_BCK | AO_MX44 | AO_MX22 | I/O | G1.6[1:0] | Bit clock | |||||||||
AU_LRCK | AO_MX45 | AO_MX23 | I/O | LR clock | ||||||||||
ADC_DATA0 | AO_MX46 | AO_MX24 | I | DATA in | ||||||||||
AU_DATA0 | AO_MX47 | AO_MX25 | O | DATA out | ||||||||||
In the schematics, an ES8316 audio ADC and DAC chip is utilized. The I2S interface signals of the ES8316 connect to position X1 of channel 0 on the SP7350. The MCLK pin of the ES8316 connects to the EXT_DAC_XCK (GPIO83) audio clock output pin of the SP7350. Additionally, the I2C interface of the ES8316 connects to I2C4 on the SP7350, with I2C4_CLK and I2C4_DATA configured to GPIO90 and GPIO91, respectively.
...