This document elucidates the application circuits associated with the SP7350. It serves as a supplementary resource to the specification of the SP7350.
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All power sources should be managed using the CM4_PWR_EN signal. Specifically, when CM4_PWR_EN is set to LOW, all power supplies, including those for the CM4 and Main power domain, should be deactivated.
Please refer to the provided power scheme for details on power control.
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Refer to the power scheme illustrated below. All powers in the main power domain should be controlled by both CM4_PWR_EN and MAIN_PWR_EN signals. Specifically, all powers in the main power domain are only turned on when both CM4_PWR_EN and MAIN_PWR_EN are set to HIGH.
It's important to note that during cold booting, CM4_PWR_EN goest to HIGH to initiate the booting process. Therefore, the default state ofMAIN_PWR_EN (when the GPIO is not yet programmed) should be HIGH to allow the CA55 to start booting.
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Typically, MAIN_PWR_EN is controlled by a GPIO in the CM4 domain. CM4 can directly set the power of the main power domain to either on or off.
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DDR Type | Max. Clock | Max. Data Rate | Max. BW (1 ch) | Max. BW (2 ch) |
|---|---|---|---|---|
LPDDR4 | 1.600 GHz | 3200 MT/s | 6.4 GB/s | 12.8 GB/s |
DDR4 | 1.333 GHz | 2666 MT/s | 5.3 GB/s | 10.7 GB/s |
LPDDR3 / DDR3 / DDR3L | 0.933 MHz | 1866 MT/s | 3.7 GB/s | 7.5 GB/s |
Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.
5.1 Data Bus and Data Strobe Signals Wiring
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Please refer to the schematics for the connection of power, address bus, data bus, and control signals of the DDR PHY. Two DDR4 SDRAM chips are utilized to form a 32-bit width data bus. Besides, the T-topology methodology is employed to route the address signals from the PHY to the two SDRAM chips.
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The VREFCA pin is linked to a reference voltage produced by a 2kΩ-to-2kΩ resistor divider with 1% accuracy, coupled with a 0.22µF bypass capacitor for decoupling. For on-die terminator calibration, the LZQ and UZQ pins should be connected to 240Ω resistors with 1% accuracy, respectively.
5.4.3 Clock Termination
Please refer to the schematics provided below. The clock signal differential pair of DDR4 SDRAM (DRAM_CLK0_T and DRAM_CLK0_C) requires AC termination with a differential impedance of 100Ω. Additionally, the T-topology methodology is employed to route the clock signals from the PHY to the two SDRAM chips.
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Please refer to the schematics for the connection of power, address bus, data bus, and control signals of DDR3 SDRAM. Two DDR3 SDRAM chips are utilized to form a 32-bit width data bus. Besides, the T-topology methodology is employed to route the address signals from the PHY to the two SDRAM chips.
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The VREFCA and VREFDQ pins are connected to a reference voltage generated by a 2kΩ-to-2kΩ resistor divider with 1% accuracy, complemented by a 0.22µF bypass capacitor for decoupling. For on-die terminator calibration, the ZQ0 and ZQ1 pins should be linked to 240Ω resistors with 1% accuracy, respectively.
5.5.3 Clock Termination
Refer to schematics below, the differential-pair clock signal of DDR3 SDRAM (DRAM_CLK0_T and DRAM_CLK0_C) requires AC termination with a differential impedance of 100Ω. Furthermore, the T-topology methodology is utilized to route the clock signal from the PHY to the two SDRAM chips.
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ILIM = 6800/6800 = 1.0 (A)
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Note that R218 and C247 are requested and defined by OTG specification. Do not alter their values.
The UPHY0_DRV5V_EN signal controls VBUS on/off states, generated by the OTG hardware of SP7350.
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17.2 MIPI-RX2 and MIPI-RX3
Note that MIPI-RX2 is not available for version A chips.
When CPIO is disabled, MIPI-RX2 and MIPI-RX3 are available for use. MIPI-RX2 supports four data and one clock lanes (4d1c) with 4 virtual channels if MIPI-RX3 is not enabled. However, if MIPI-RX3 is enabled, both MIPI-RX2 and RX3 support two data and one clock lanes (2d1c). Each data lane can transmit up to 1.5 Gbps. Please refer to the table for pin sharing between MIPI-RX2, MIPI-RX3, and CPIO.
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