This document elucidates the application circuits associated with the SP7350. It serves as a supplementary resource to the specification of the SP7350.
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All power sources should be managed using the CM4_PWR_EN signal. Specifically, when CM4_PWR_EN is set to LOW, all power supplies, including those for the CM4 and Main power domain, should be deactivated.
Please refer to the provided power scheme for details on power control.
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The seven bootstrap pins encompass a variety of functions pertaining to boot device selection, CA555 JTAG/SWD interface activation, and chip test mode activation. Refer to the table below for the definition of each bootstrap pin regarding boot device selection:
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When IV_MX2 is set to LOW, the SP7350 enters test mode, designated for internal use only. Likewise, when IV_MX1 is set to LOW, the CA55 JTAG/SWD interface pins are activated. IV_MX0 remains unused.
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Refer to the power scheme illustrated below. All powers in the main power domain should be controlled by both CM4_PWR_EN and MAIN_PWR_EN signals. Specifically, all powers in the main power domain are only turned on when both CM4_PWR_EN and MAIN_PWR_EN are set to HIGH.
It's important to note that during cold booting, CM4_PWR_EN goest to HIGH to initiate the booting process. Therefore, the default state ofMAIN_PWR_EN (when the GPIO is not yet programmed) should be HIGH to allow the CA55 to start booting.
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Typically, MAIN_PWR_EN is controlled by a GPIO in the CM4 domain. CM4 can directly set the power of the main power domain to either on or off.
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DDR Type | Max. Clock | Max. Data Rate | Max. BW (16 bits) | Max. BW (32 bits) |
|---|---|---|---|---|
LPDDR4 | 1.600 GHz | 3200 MT/s | 6.4 GB/s | 12.8 GB/s |
DDR4 | 1.333 GHz | 2666 MT/s | 5.3 GB/s | 10.7 GB/s |
LPDDR3 / DDR3 / DDR3L | 0.933 MHz | 1866 MT/s | 3.7 GB/s | 7.5 GB/s |
Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.
5.1 Data Bus and Data Strobe Signals Wiring
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The SP7350 supports SPI-NAND flash for booting. To boot from an SPI-NAND flash, set the bootstrap pins IV_MX[6:2] to [1 1 1 0 1]. The SP7350 supports either 2k-sector with 1 or 2 planes or 4k-sector with 1 plane. When using a 1.8V flash chip, the maximum clock frequency is 153 MHz. It's advisable to use a 1.8V flash chip for optimal high-speed operation.
Special Note:
NAND flash memory in the market is categorized into SLC (Single-Level Cell) and MLC (Multi-Level Cell) types. MLC NAND has a higher likelihood of developing bad cells. It's important to note that the Linux ubifs (sorted block image file system) subsystem does not support MLC NAND. Therefore, if you plan to use NAND flash as the primary storage (boot) device, it is recommended to opt for SLC NAND flash.
10.1 SPI-NAND Interface of SP7350
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The SP7350 supports booting from 8-bit NAND flash. To boot from an 8-bit NAND flash, set the bootstrap pins IV_MX[6:2] to [1 0 0 0 1]. The SP7350 is compatible with 2k-sector, 4k-sector, or 8k-sector NAND flash. For optimal high-speed performance, it's recommended to use a 1.8V VCCQ power supply.
Special Note:
NAND flash memory in the market is categorized into SLC (Single-Level Cell) and MLC (Multi-Level Cell) types. MLC NAND has a higher likelihood of developing bad cells. It's important to note that the Linux ubifs (sorted block image file system) subsystem does not support MLC NAND. Therefore, if you plan to use NAND flash as the primary storage (boot) device, it is recommended to opt for SLC NAND flash.
11.1 8-bit NAND Interface of SP7350
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ILIM = 6800/6800 = 1.0 (A)
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Note that R218 and C247 are requested and defined by OTG specification. Do not alter their values.
The UPHY0_DRV5V_EN signal controls VBUS on/off states, generated by the OTG hardware of SP7350.
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17.2 MIPI-RX2 and MIPI-RX3
Note that MIPI-RX2 is not available for version A chips.
When CPIO is disabled, MIPI-RX2 and MIPI-RX3 are available for use. MIPI-RX2 supports four data and one clock lanes (4d1c) with 4 virtual channels if MIPI-RX3 is not enabled. However, if MIPI-RX3 is enabled, both MIPI-RX2 and RX3 support two data and one clock lanes (2d1c). Each data lane can transmit up to 1.5 Gbps. Please refer to the table for pin sharing between MIPI-RX2, MIPI-RX3, and CPIO.
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It's recommended to include ESD protection diodes for MIC_RIN2, SPK1_N, and SPK1_P signals if the devices are human-accessible.
20. CA55 JTAG and SWD Interface
The SP7350 board supports the JTAG and SWD ICE interface interfaces for Cortex A55 (CA55). This interface enables Both interfaces allow developers to perform debug their target systems in real-time debugging by connecting to the CA55 processor's . JTAG (Joint Test Action Group) is the traditional interface, while SWD (Serial Wire Debug) is a two-wire protocol designed specifically for ARM processors, offering an alternative when pin resources are limited or PCB layout is constrained.
20.1 CA55 JTAG and SWD Pins
The For JTAG, the interface pins are mapped to GPIO13 to GPIO17, corresponding to the TRST_N, TMS, TCK, TDI, and TDO signals of JTAG. For SWD, the pins are GPIO14, GPIO15, and GPIO17, corresponding to SWDIO, SWCLK, and SWO signals.
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To activate the JTAG/SWD interface, users should configure G1.1[8] to 1 or set bootstrap pin IV_MX[1] to 0. Please note that the JTAG/SWD interface pins share functionality with RGMII pins and cannot be used simultaneously.
20.2 CA55 JTAG and SWD Pin-header
Referring to the schematics below, the standard JTAG/SWD connector is a 2x10-pin 100mil-pitch pin-header. Pin 1 serves as the reference voltage for JTAG/SWD signals, while Pin 2 provides optional VCC power. The JTAG_nSRST signal (low-active), derived from the RESETB signal, functions as the system reset. It's important to note that the CA55 JTAG/SWD signals operate at 1.8V.
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21. CM4 JTAG
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Interface
The SP7350 also supports the JTAG and SWD ICE interfaces interface for Cortex M4 (CM4). Both interfaces allow This interface enables developers to debug their target systems in perform real-time . JTAG is the traditional interface, while SWD (Serial Wire Debug) is a two-wire protocol designed specifically for ARM processors, offering an alternative when pin resources are limited or PCB layout is constraineddebugging by connecting to the CM4 processor's JTAG interface.
21.1 CM4 JTAG
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Pins
For JTAG, the The interface pins are GPIO88 to mapped to GPIO88, GPIO89, GPIO90, GPIO92 and GPIO93, corresponding to the TRST_N, TMS, TCK, TDI, and TDO signals . For SWD, the pins are GPIO89, GPIO90, and GPIO93, corresponding to SWDIO, SWCLK, and SWDO signals.of JTAG.
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To activate the JTAG interface, users should configure G1.5[0] to 1.
21.2 CM4 JTAG
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Pin-header
Referring to the schematics below, the standard JTAG /SWD connector is a 2x10-pin 100mil-pitch pin-header. Pin 1 provides the reference voltage for JTAG signals, and Pin 2 offers optional VCC power. Similar to CA55, the CM4_JTAG_nSRST signal (low-active) for system reset is derived from the RESETB signal. Note that the CM4 JTAG signals operate at 1.8V.
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