14.1 Introduction
Ethernet is a computer local area network technology. IEEE's IEEE 802.3 standard sets the technical standard for Ethernet, which specifies the content of the connection, electronic signal and medium access layer agreements including the physical layer. Ethernet is the most popular area network technology currently used, replacing other regional network standards such as Token Ring, FDDI and ARCNET. The standard topology of Ethernet is a bus topology, but the current fast Ethernet (100BASE-T, 1000BASE-T standard) used switch/hub in network connection and organization to increase the network speed, use efficiency and minimize conflicts. As a result, the topology of the Ethernet network becomes a star topology.
Ethernet implements the idea of transmitting information to multiple nodes in the radio system on the network. Each node must obtain cables or channels to transmit information. Each node has a globally unique 48-bit address, which is the MAC address assigned by the manufacturer to the Network Interface Card (NIC). The MAC address is used to ensure that all nodes on the Ethernet can authenticate each other. Because Ethernet is so common, many manufacturers integrate Ethernet cards directly into their motherboards.
This section describes the Ethernet Switch and its associated operational modes. The SP7021 supports a layer 2 (L2) switch (L2SW) with 2 Ethernet ports and 1 SoC port (also called CPU port or NIC port) which acts like a NIC card connected to the 3rd port of switch. The base address for Ethernet Switch Control and Status Registers (CSR) is 0x9C108000 and all registers in the memory map address ranges from 0x9C108000 to 0x9C10827F.
Table 14-1. shows the key feature of Ethernet hardware (L2SW IP) of SP7021.
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Fields | Fields name | Description |
Bit 31 | daisy_mode_chg | Daisy mode change flag |
Bit 23 | appending_error_0 | IP checksum append error |
Bit 22 | Watchdog1_tmr_expired | Watchdog1_tmr_expired |
Bit 21 | Watchdog0_tmr_expired | Watchdog0_tmr_expired |
Bit 20 | has_intruder | Intruder alert |
Bit 19 | port_st_chg | Port status change |
Bit 18 | bc_storm | BC storm |
Bit 17 | must_drop_lan | Global queue exhausted The must_drop_set_th refer to register Group0.47 flow_ctrl_th3[11:8]. |
Bit 16 | global_que_full | Global queue full (refer to register Group0.2 fl_cntl_th[23:16]). |
Bit 15 | soc_tx_pause_on_0 | Soc port0 transmit pause on |
Bit 14 | soc_qfull_0 | Soc port0 out queue full (Refer to register Group0.3 cpu_fl_cntl_th[15:8]). |
Bit 9 | lan_que_full[1] | port1 out queue full (Refer to register Group0.3 cpu_fl_cntl_th[7:0]). |
Bit 8 | lan_que_full[0] | port0 out queue full (Refer to register Group0.3 cpu_fl_cntl_th[7:0]). |
Bit 7 | L_desc_full_0 | Low priority descriptor full for soc port0 |
Bit 6 | H_desc_full_0 | High priority descriptor full for soc port0 |
Bit 5 | Rx_l_done_0 | Receive low priority descriptor done for soc port0 |
Bit 4 | Rx_h_done_0 | Receive high priority descriptor done for soc port0 |
Bit 3 | Tx_l_done_0 | Transmit low priority descriptor done for soc port0 |
Bit 2 | Tx_h_done_0 | Transmit high priority descriptor done for soc port0 |
Bit 1 | Tx_desc_err_sa_0 | TX descriptor error for soc port0 |
Bit 0 | Rx_desc_err_sa_0 | RX descriptor error for soc port0 |
Table 14-2 Group0.0 sw_int_status_0 register.
Fields | Fields name | Description |
Bit 23 | appending_error_1 | IP checksum append error |
Bit 15 | soc_tx_pause_on_1 | Soc port1 transmit pause on |
Bit 14 | soc_qfull_1 | Soc port1 out queue full (Refer to register Group0.3 cpu_fl_cntl_th[15:8]). |
Bit 7 | L_desc_full_1 | Low priority descriptor full for soc port1 |
Bit 6 | H_desc_full_1 | High priority descriptor full for soc port1 |
Bit 5 | Rx_l_done_1 | Receive low priority descriptor done for soc port1 |
Bit 4 | Rx_h_done_1 | Receive high priority descriptor done for soc port1 |
Bit 3 | Tx_l_done_1 | Transmit low priority descriptor done for soc port1 |
Bit 2 | Tx_h_done_1 | Transmit high priority descriptor done for soc port1 |
Bit 1 | Tx_desc_err_sa_1 | TX descriptor error for soc port1 |
Bit 0 | Rx_desc_err_sa_1 | RX descriptor error for soc port1 |
Table 14-3 Group0.52 sw_int_status_1 register.
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