15. Ethernet Switch

15.1 Introduction

Ethernet is a computer local area network technology. IEEE's IEEE 802.3 standard sets the technical standard for Ethernet, which specifies the content of the connection, electronic signal and medium access layer agreements including the physical layer. Ethernet is the most popular area network technology currently used, replacing other regional network standards such as Token Ring, FDDI and ARCNET. The standard topology of Ethernet is a bus topology, but the current fast Ethernet (100BASE-T, 1000BASE-T standard) used switch/hub in network connection and organization to increase the network speed, use efficiency and minimize conflicts. As a result, the topology of the Ethernet network becomes a star topology.
Ethernet implements the idea of transmitting information to multiple nodes in the radio system on the network. Each node must obtain cables or channels to transmit information. Each node has a globally unique 48-bit address, which is the MAC address assigned by the manufacturer to the Network Interface Card (NIC). The MAC address is used to ensure that all nodes on the Ethernet can authenticate each other. Because Ethernet is so common, many manufacturers integrate Ethernet cards directly into their motherboards.
This section describes the Ethernet Switch and its associated operational modes. The SP7021 supports a layer 2 (L2) switch (L2SW) with 2 Ethernet ports and 1 SoC port (also called CPU port or NIC port) which acts like a NIC card connected to the 3rd port of switch. The base address for Ethernet Switch Control and Status Registers (CSR) is 0x9C108000 and all registers in the memory map address ranges from 0x9C108000 to 0x9C10827F.
Table 15-1. shows the key feature of Ethernet hardware (L2SW IP) of SP7021.

Table 15-1. Key feature of Ethernet Switch (L2SW IP) of SP7021

15.2 Function Diagram

A generalized function diagram of Ethernet L2SW of SP7021 is shown in Figure 15-1.

Figure 15-1 Ethernet Switch (L2SW IP) Block  Diagram
Here are descriptions of each block:

 

• sw_port: Switch port0/port1. 10M/100M Ethernet port transceiver.

• sw_dt_mng: Switch data buffer manager.

• soc_port: Soc port, CPU can receive packet from or transmit packet to switch through this port.

• sw_lk_mng: Link manager. It schedules the packet transmit and receive for port0/port1/soc port.

• sw_at_mng: Address table manager. It controls the address table learning and searching.

• sw_at_age: Address table aging control.

• sw_at_cfg: Address table configuration by CPU.

• sw_at_lkup: Address table lookup by CPU.

• Led: LED control. 3 LED for each port.

• bishop: Memory BIST control.

• sp_reg: Switch register file.

• smi_master: Serial management interface master. Switch can polling Ethernet PHY registers through SMI interface.

• Debug_sw_core: Debug control. 16 bits debug probe are provided for debug purpose.

 

15.3 Data Structure

15.3.1 Descriptors of Ethernet

The Layer 2 Switch (L2SW) uses descriptors to control transmission and reception of packets between CPU interface and 2 Ethernet ports. Software allocates and initializes memory for descriptors. Descriptors consists of many fields which instructs Ethernet hardware where and how to get or store data for transmission and reception. The Ethernet hardware reads descriptors and uses the allocated memory to access data. Descriptors should be allocated continuously in the memory by software called descriptor queue and the Ethernet hardware uses these descriptors in order. Figure 15-2 illustrates the relationship between descriptors and data buffers.

Figure 15-2 Descriptors of L2SW

15.3.2 TX Descriptor

Ethernet hardware supports 2 descriptors queue for transmission and 2 descriptors queue for reception. One descriptor queue is for low-priority packets and the other is for high-priority packets. Packets with high-priority tagged will be received and placed on high-priority queue and other packets will be received and placed on low-priority queue during reception. For transmission, software decides which queue the packets will be placed in. Figure 15-3 shows the detailed field definition of transmission (TX) descriptor.

Figure 15-3 Field definition of TX descriptor
Here are detailed description of each field:

• own_bit:

          0: The descriptor is owned by software. The Ethernet hardware sets own-bit to 0 when transmission is done or error happens.
          1: The descriptor is owned by Ethernet hardware. Software sets own-bit to 1 when a descriptor is ready for Ethernet hardware fetching.

• error_code:

• start_of_pkt:

          1: The first descriptor of the packet;
          0: The middle/last descriptor of the packet.

• end_of_pkt:

          1: The last descriptor of the packet;
          0: The middle/first descriptor of the packet.

• force_dp: force destination port

          [18]: force forward to port 0
          [19]: force forward to port 1

• to_vlan: the vlan member set index, the packet forward to the designated VLAN group.

• pkt_length: tx_len_r, the length of the current packet

• ring_end: end of the descriptor ring

• append_ip_sum: append IP checksum

• append_tcpudp_sum: append tcp/udp checksum (not implemented yet)

• buf2_length: buf2 length. Each descriptor can support two buffers, if the tx_length > buf1_length, then get the rest data from buf2.

• buf1_length: buf1 length.

• buf1_addr: buf1 address.

• buf2_addr: buf2 address.

 

15.3.3 RX Descriptor

Figure 15-4 shows the detailed field definition of reception (RX) descriptor.

Figure 15-4 Field definition of RX descriptor
Here are detailed description of each field:

• own_bit:

          0: The descriptor is owned by software. The Ethernet hardware sets own-bit to 0 when receiving is done or error.
          1: The descriptor is owned by Ethernet hardware. Software sets own-bit to 1 when a descriptor is ready for Ethernet hardware fetching.

• error_code:

• tcpudp_chksum_fail: (not implemented yet)

          1: The tcp/udp frame checksum error.
          0: The tcp/udp frame checksum ok.

• proxy:

          1:The mac address of soc port has been learned into the Address Table when switch transmit the packet to soc port.
          0:The mac address of soc port hasn't been learned into the Address Table while switch transmit the packet to soc port.

• protocol:

          00: IPv4 packet
          01: PPPoE packet

• others: reserved

• vlan_tag:

          1: VLAN tagged frame
          0: non VLAN tagged frame

• ip_chksum_fail:

          1: The IP frame checksum error
          0: The IP frame checksum ok.

• route_type:

          00: UC
          01: MC
          10: BC
          11: RMC

• pkt_sp:

          000: from port0
          001: from port1
          110: soc0 loopback
          101: soc1 loopback

• Others: reserved

• pkt_lenth: length of current packet

• ring_end: end of the descriptor ring

• buf2_length: buf2 length. Each descriptor can support two buffers, if the rx_len_r > buf1_length, then put the rest data to buf2.

• buf1_length: buf1 length.

• buf1_addr: buf1 address.

• buf2_addr: buf2 address.

 

15.4 Ethernet Switch Function with Address Table

The switch used in the Ethernet network can increase the available bandwidth of the network, and can also analyze the MAC address of the source end and the destination end according to the sent network packet, and create a MAC address table, and the network packet is correctly forwarded by such a MAC address table.
Although the switch is the second layer operating in the network seven-layer architecture, due to the switch has a higher speed internal structure and a larger number of interfaces, so it can provide more network traffic compared with the traditional gateway.
Regarding the learning of MAC addresses, the switch will listen to the incoming frames from their peers (called the Frame through the network packet of the switch), detect the source MAC address of these data, and recorded the correspondence of the MAC address and port number in the local MAC database. This MAC database is usually called MAC Address Table.
When the switch receives the Frame again, it will first go to the MAC database to see which node to go to the machine specified by the destination MAC address. If the destination MAC address can be found in the MAC database, then This Frame will only be forwarded from the learned port. If such a correspondence is not found in the MAC database, the Frame will be forwarded from all other ports (except sources).
SP7021 can supports up to 1K MAC address table entries. Figure 15-5 shows the address table format.

Figure 15-5 Field definition of address table
Here are detailed description of each field:

• mc_ingr – enable checking the destined port and local port are in the same group for reserved MC.

• Proxy - a packet from CPU port (SoC Port or called Port 3)

  • Look up the address table. If the SA is (cpu port=0 or proxy =1)

  • Add or update proxy 1 when learning.

  • When LAN port receiving a packet.

  • Look up the address table.

  • If the DA (proxy bit ==1), then add a proxy bit ==1 to link table.

  • AHB port transmitting a packet to Port3 will add a proxy bit to descriptor.

• Age – aging bit – The field will be 001 when a valid address is learned. It will increase by one. Once the 60 sec counter pulse is reached. When the field = 110 and the 60 sec counter pulse comes, it will wrap to 000 and the address will be aged out.

• Vid_index – VLAN member set index field.

• soc0_port – the learned port is soc0 port

• soc1_port – the learned port is soc1 port

• Reserved for further usage

• Port map – the learned port bit map.

• MAC [38:0] – the MAC address.

 

15.5 Three Operation Modes

Ethernet driver of SP-7021 supports 3 operation modes:

1. An NIC with daisy-chain mode

2. Dual NIC mode

3. An NIC with daisy-chain mode 2

In "An NIC with daisy-chain mode", Ethernet driver creates one net-device interface (ex: eth0). The net-device interface is connected to two LAN ports (two RJ45 sockets) via L2 switch. In this mode, a packet from one LAN port will be either forwarded to net-device interface (eht0) if its destination address matches MAC address of net-device interface (eth0), or forwarded to other LAN port. A packet from net-device interface (eth0) will be forwarded to a LAN port if its destination address is learnt by L2 switch, or forwarded to both LAN ports if its destination has not been learnt yet. Figure 15-6 illustrates the packets flow in this mode.

Figure 15-6 Packets flow in "An NIC with daisy-chain" mode
In "Dual NIC mode", Ethernet driver creates two net-device interfaces (ex: eth0 and eth1). Each has its dedicated LAN port. Packets will not be forwarded between two ports, unless you run some bridge utilities manually. Refer to Figure 15-7, packets from eth0 will be always forwarded to LAN port 0 and packets from LAN port 0 will be always forwarded to eth0. The same theory is applied for eth1 and LAN port 1.

Figure 15-7 Packets flow in "Dual NIC" mode
"An NIC with daisy-chain mode 2" is similar to "An NIC with daisy-chain mode". The difference is that a packet from net-device interface (eth0) will be always forwarded to both LAN ports. Learning function of L2 switch is turned off in this mode. This means L2 switch will never learn the source address of a packet. So, it always forward packets to both LAN ports. This mode works like you have 2-port Ethernet hub.

15.6 L2SW Interrupts

The L2SW interrupt events are connected to the same interrupt vector, please refer to figure 15-8. These events generate an interrupt if the corresponding "Enable Control Bit" is set. The detail L2SW interrupt information refer to Ethernet Group0.0 sw_int_status_0 register for port0 and Group0.52 sw_int_status_1 register for port1. The enable register is Ethernet Group0.0 sw_int_mask_0 register for port0 and Group0.53 sw_int_mask_1 register for port1.

Figure 15-8 L2SW Interrupt Tree
Table 15-2/15-3 shows the Group0.0 sw_int_status_0/Group0.52 sw_int_status_1 registers for each interrupt flag description.

Table 15-2 Group0.0 sw_int_status_0 register.

Table 15-3 Group0.52 sw_int_status_1 register.

15.7 Registers Map

15.7.1 Registers Memory Map