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Field Name | Bit | Access | Description |
| reserved | 31:0 | RO | RESERVED |
196.6 Debug register (osd bus monitor lreserved)
Address: 0x9C006218
Reset: 0x0
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Field Name | Bit | Access | Description |
| MON TAREGT BUS DATA Lreserved | 31:0 | RO | Shown BUS data [31:0].Setting by ADDR.9 and |
196.7 Debug register (osd bus monitor hreserved)
Address: 0x9C00621C
Reset: 0x0
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Field Name | Bit | Access | Description | |
| MON TAREGT BUS DATA Hreserved | 31:0 | RO | Shown BUS data [63:32].Setting by ADDR.9 and Debug Register 需要嗎 ? | RESERVED |
196.8 OSD Request Control Register (osd req ctrl)
Address: 0x9C006220
Reset: 0x0000 8020
Field Name | Bit | Access | Description |
| reserved | 31:16 | RO | RESERVED |
| OSD urg regu en | 15 | RW | osd vblank urgent regulator function enable |
| reserved | 14:9 | RO | RESERVED |
| OSD urg th | 8:0 | RW | osd fifo urgent threshold 0x1FF..0x100: always urgent 0x0: no urgent request other: urgent when the fifo-grant-count smaller than this value unit: 32bytes, bit[1:0] will be discarded |
196.9 Debug register (osd debug cmd lockreserved)
Address: 0x9C006224
Reset: 0x0
Field Name | Bit | Access | Description |
| reserved | 31:16 | RO | RESERVED |
CMD NUM LOCK DATAreserved | 15:0 | RW | Select which DRAM data would be caught to ADDR.22 ADDR.25 Set 0 means to catch DRAM data of 1st command. To use this feature with ADDR.10 Debug Register 需要嗎 ?RESERVED |
196.10 Debug register (osd debug burst lockreserved)
Address: 0x9C006228
Reset: 0x0
Field Name | Bit | Access | Description | |
| reserved | 31:6 | RO | RESERVED | |
| BURST NUM LOCK DATAreserved | 5:0 | RW | Select which DRAM data would be caught to Debug Register 需要嗎 ? | RESERVED |
196.11 Debug register (osd debug xlen lockreserved)
Address: 0x9C00622C
Reset: 0x0
Field Name | Bit | Access | Description |
| reserved | 31:13 | RO | RESERVED |
| PIX CNT LOCK LBreserved | 12:0 | RW | Define when the LB information would be shown in ADDR.26[9:0] This reigster means OSD ouput pixel counter. To use this feature with ADDR.12 Debug Register 需要嗎 ?RESERVED |
196.12 Debug register (osd debug ylen lockreserved)
Address: 0x9C006230
Reset: 0x0
Field |
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Field Name | Bit | Access | Description | |
| reserved | 31:12 | RO | RESERVED | LINE CNT LOCK LB|
reserved | 11:0 | RW | Define when the LB information would be shown in ADDR.26[9:0] This reigster means OSD ouput line counter. To use this feature with ADDR.11 Debug Register 需要嗎 ? | RESERVED |
196.13 Debug register (osd debug queue lock)
Address: 0x9C006234
Reset: 0x0
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Field Name | Bit | Access | Description |
| reserved | 31:28 | RO | RESERVED |
| OSD NON FETCH LEN3 | 27:16 | RW | Vertical length of non-fetching region 3 |
| reserved | 15:12 | RO | RESERVED |
| OSD NON FETCH ST3 | 11:0 | RW | Vertical start position of non-fetching region 3 |
196.26 Debug register (osd bus statusreserved)
Address: 0x9C006268
Reset: 0x0
Debug Register 需要嗎 ?
Field Name | Bit | Access | Description | |
| reserved | 31:14 | RO | RESERVED | |
MON FRAME END LB ERROR reserved | 13 | RUW | Display done, LB still exist data | MON FRAME END BUS ERRORRESERVED |
reserved | 12 | RUW | Display done, BUS still exist uncompleted handshakingRESERVED | |
reserved | 11:10 | RO | RESERVED | |
MON TARGET LB DEPTHreserved | 9:0 | RUW | Shown the status of LB depth by setting ADDR.11 and |
196.27 OSD 3D h offset (osd 3d h offset)
Address: 0x9C00626C
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Field Name | Bit | Access | Description |
| reserved | 31:4 | RO | RESERVED |
VINT SRC DECIMATION | 3:2 | RW | VINT src decimation |
HINT SRC DECIMATION | 1:0 | RW | HINT src decimation |
196.30 Debug register (osd bus time 0reserved)
Address: 0x9C006278
Reset: 0x0
Debug Register 需要嗎 ?
Field Name | Bit | Access | Description |
reserved | 31:16 | RO | RESERVED |
BUS REQ GNT CYCLEreserved | 15:0 | RUW | Slowest clock cycle of REQ to GNT |
196.31 Debug register (osd mbus time 1reserved)
Address: 0x9C00627C
Reset: 0x0
Debug Register 需要嗎 ?
Field Name | Bit | Access | Description |
reserved | 31:16 | RO | RESERVED |
BUS GNT DOE CYCLEreserved | 15:0 | RUW | Slowest clock cycle of GNT to DONE |
RGST Table Group 199 VPOST: Video Post
199.0 VPOST Config Register 1 (vpost config1)
Address: 0x9C006380
Reset: 0x1000
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