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Field Name | Bit | Access | Description |
| Mask bit | 31:16 | RW | Write valid bit for each LSB 16 bits The 16 bits map to corresponding LSB 16bits. Write 1 to valid the corresponding bit writing. |
| Reserved | 15 | RW | RESERVED |
| MO PLLE CLKOUT DIV | 14 | RW | PLL Clock output divider 0x0: PLL clock output 0x1: PLL clock div 2 output |
| MO PLLE EN FCK2P5M | 13 | RW | FCK2P5M clock enable 0x0: disalbe 0x1: enable |
| MO PLLE EN FCK25M | 12 | RW | FCK25M clock enable 0x0: disalbe 0x1: enable |
| MO PLLE EN FCK | 11 | RW | FCK112P2M FCK112P5M clock enable 0x0: disalbe 0x1: enable |
| MO PLLE RSV IN | 10:7 | RW | PLLE Resevred Bit |
| MO PLLE PD N | 6 | RW | Power down signal 0x0: disable PLL (power down) 0x1: enable PLL |
| MO PLLE ICP | 5:3 | RW | ICP current selection of CHP block 0x0: ICP=5uA 0x1: ICP=10uA 0x2: ICP=15uA 0x3: ICP=20uA 0x4: ICP=25uA 0x6: ICP=35uA 0x7: ICP=40uA |
| MO PLLE BP | 2 | RW | Bypass mode enable BP=1, FCKOUT=CLK27 (Only can be enabled when PD N=1) |
| MO PLLE BANK | 1:0 | RW | PLLE frequency selection 0x0:2.338GHz/V 0x1:2.617GHz/V 0x2: 2.886GHz/V 0x3: 3.103GHz/V |
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