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Field NameBitAccessDescription
Mask bit31:16RWWrite valid bit for each LSB 16 bits
The 16 bits map to corresponding LSB 16bits. Write 1 to valid the corresponding bit writing
PERI1 CLKEN15RWTPI PERI1 Hardware Clock Enable
0: Disable
1: Enable (default)
UMCTL2 CLKEN14RWSDCTRL0 Hardware Clock Enable
0: Disable
1: Enable (default)

A926 CLKEN

13

RW

A926 Hardware Clock Enable
0: Disable
1: Enable (default)

Reserved

12

RW

RESERVED

PERI0 CLKEN

11

RW

PERI0 Hardware Clock Enable
0: Disable
1: Enable (default)

SDCTRL0 CLKEN

10

RW

SDCTRL Hardware Clock Enable
0: Disable
1: Enable (default)

SPIFL CLKEN

9

RW

SPIFL Hardware Clock Enable
0: Disable
1: Enable (default)

RBUS L00 CLKEN

8

RW

RBUS L00 Hardware Clock Enable
0: Disable
1: Enable (default)

BR CLKEN

7

RW

BR Hardware Clock Enable
0: Disable
1: Enable (default)

NOC CLKEN

6

RW

NOC Hardware Clock Enable
0: Disable
1: Enable (default)

Reserved

5

RW

RESERVED

IOP CLKEN

4

RW

IOP Hardware Clock Enable
0: Disable
1: Enable (default)

IOCTL CLKEN

3


IO CTL Hardware Clock Enable
0: Disable
1: Enable (default)

RTC CLKEN

2

RW

RTC Hardware Clock Enable
0: Disable
1: Enable (default)

Reserved

1


RESERVED

SYSTEM CLKEN

0

RW

SYSTEM Hardware Clock Enable
0: Disable
1: Enable (default)

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Field NameBitAccessDescription
Mask bit31:16RWWrite valid bit for each LSB 16 bits
The 16 bits map to corresponding LSB 16bits. Write 1 to valid the corresponding bit writing

PERI1 GCLKEN

15

RW

TPI PERI1 Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

UMCTL2 GCLKEN

14

RW

SDCTRL0 Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

A926 GCLKEN

13

RW

A926 Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

Reserved

12

RW

RESERVED

PERI0 GCLKEN

11

RW

PERI0 Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

SDCTRL0 GCLKEN

10

RW

SDCTRL Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

SPIFL GCLKEN

9

RW

SPIFL Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

RBUS L00 GCLKEN

8

RW

RBUS L00 Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

BR GCLKEN

7

RW

BR Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

NOC GCLKEN

6

RW

NOC Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

Reserved

5

RW

Reserved

IOP GCLKEN

4

RW

IOP Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

IOCTL GCLKEN

3

RW

IO CTL Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

RTC GCLKEN

2

RW

RTC Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

Reserved1RWreserved
SYSTEM GCLKEN0RWSYSTEM Hardware Clock-Gating Enable
0: Disable
1: Enable (default)

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