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14.1 Introduction

Ethernet is a computer local area network technology. IEEE's IEEE 802.3 standard sets the technical standard for Ethernet, which specifies the content of the connection, electronic signal and medium access layer agreements including the physical layer. Ethernet is the most popular area network technology currently used, replacing other regional network standards such as Token Ring, FDDI and ARCNET. The standard topology of Ethernet is a bus topology, but the current fast Ethernet (100BASE-T, 1000BASE-T standard) used switch/hub in network connection and organization to increase the network speed, use efficiency and minimize conflicts. As a result, the topology of the Ethernet network becomes a star topology.
Ethernet implements the idea of transmitting information to multiple nodes in the radio system on the network. Each node must obtain cables or channels to transmit information. Each node has a globally unique 48-bit address, which is the MAC address assigned by the manufacturer to the Network Interface Card (NIC). The MAC address is used to ensure that all nodes on the Ethernet can authenticate each other. Because Ethernet is so common, many manufacturers integrate Ethernet cards directly into their motherboards.
This section describes the Ethernet Switch and its associated operational modes. The SP7021 supports a layer 2 (L2) switch (L2SW) with 2 Ethernet ports and 1 SoC port (also called CPU port or NIC port) which acts like a NIC card connected to the 3rd port of switch. The base address for Ethernet Switch Control and Status Registers (CSR) is 0x9C108000 and all registers in the memory map address ranges from 0x9C108000 to 0x9C10827F.
Table 14-1. shows the key feature of Ethernet hardware (L2SW IP) of SP7021.

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Fields	Fields name	Description
Bit 31	daisy_mode_chg	Daisy mode change flag
Bit 23	appending_error_0	IP checksum append error
Bit 22	Watchdog1_tmr_expired	Watchdog1_tmr_expired
Bit 21	Watchdog0_tmr_expired	Watchdog0_tmr_expired
Bit 20	has_intruder	Intruder alert High active to indicate an unsecured packet is coming into a secure port.
Bit 19	port_st_chg	Port status change
Bit 18	bc_storm	BC storm High active to indicate the broadcast storm.
Bit 17	must_drop_lan	Global queue exhausted The global queue (data ram) space is not enough and all the packets from port0&1 will be dropped. The must_drop_set_th refer to register Group0.47 flow_ctrl_th3[11:8].
Bit 16	global_que_full	Global queue full The global queue space reaches the flow control threshold fc_set_th (refer to register Group0.2 fl_cntl_th[23:16]).
Bit 15	soc_tx_pause_on_0	Soc port0 transmit pause on
Bit 14	soc_qfull_0	Soc port0 out queue full The out queue for soc port0 is reaches the threshold cpu_th (Refer to register Group0.3 cpu_fl_cntl_th[15:8]).
Bit 9	lan_que_full[1]	port1 out queue full The out queue for port1 is reaches the threshold port_th (Refer to register Group0.3 cpu_fl_cntl_th[7:0]).
Bit 8	lan_que_full[0]	port0 out queue full The out queue for port0 is reaches the threshold port_th (Refer to register Group0.3 cpu_fl_cntl_th[7:0]).
Bit 7	L_desc_full_0	Low priority descriptor full for soc port0
Bit 6	H_desc_full_0	High priority descriptor full for soc port0
Bit 5	Rx_l_done_0	Receive low priority descriptor done for soc port0
Bit 4	Rx_h_done_0	Receive high priority descriptor done for soc port0
Bit 3	Tx_l_done_0	Transmit low priority descriptor done for soc port0
Bit 2	Tx_h_done_0	Transmit high priority descriptor done for soc port0
Bit 1	Tx_desc_err_sa_0	TX descriptor error for soc port0
Bit 0	Rx_desc_err_sa_0	RX descriptor error for soc port0

Table 14-2 Group0.0 sw_int_status_0 register.

Fields	Fields name	Description
Bit 23	appending_error_1	IP checksum append error
Bit 15	soc_tx_pause_on_1	Soc port1 transmit pause on
Bit 14	soc_qfull_1	Soc port1 out queue full The out queue for soc port0 is reaches the threshold cpu_th (Refer to register Group0.3 cpu_fl_cntl_th[15:8]).
Bit 7	L_desc_full_1	Low priority descriptor full for soc port1
Bit 6	H_desc_full_1	High priority descriptor full for soc port1
Bit 5	Rx_l_done_1	Receive low priority descriptor done for soc port1
Bit 4	Rx_h_done_1	Receive high priority descriptor done for soc port1
Bit 3	Tx_l_done_1	Transmit low priority descriptor done for soc port1
Bit 2	Tx_h_done_1	Transmit high priority descriptor done for soc port1
Bit 1	Tx_desc_err_sa_1	TX descriptor error for soc port1
Bit 0	Rx_desc_err_sa_1	RX descriptor error for soc port1

Table 14-3 Group0.52 sw_int_status_1 register.

14.7

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Registers Map

14.7.1 Registers Memory Map

Address	Group No.	Register Name	Description	Reset Default
0x9C1080000x9C108000	G0.0	sw int status 0	Interrupt Status 0	0x0000_0000
0x9C1080040x9C108004	G0.1	sw int mask 0	Interrupt Mask 0	0x80ff_c3ff
0x9C1080080x9C108008	G0.2	fl cntl th	Flow Control Threshold	0x8878_5a46
0x9C10800C0x9C10800C	G0.3	cpu fl cntl th	CPU Port Flow Control Threshold	0x8878_120c
0x9C1080100x9C108010	G0.4	pri fl cntl	Priority Flow Control	0xf338 0000
0x9C1080140x9C108014	G0.5	vlan pri th	Vlan Priority Threshold	0x0000 0400
0x9C1080180x9C108018	G0.6	En tos bus	TOS Enable	0x0000_0000
0x9C10801C0x9C10801C	G0.7	TOS map0	TOS Map 0	0x0000_0000
0x9C1080200x9C108020	G0.8	TOS map1	TOS Map 1	0x0000_0000
0x9C1080240x9C108024	G0.9	TOS map2	TOS Map 2	0x0000_0000
0x9C1080280x9C108028	G0.11	TOS map3	TOS Map 3	0x0000_0000
0x9C10802C0x9C10802C	G0.11	TOS map4	TOS Map 4	0x0000_0000
0x9C1080300x9C108030	G0.12	TOS map5	TOS Map 50x0000_0000
0x9C108034TOS	G0.13	TOS map6	TOS Map 6	0x0000_0000
0x9C1080380x9C108038	G0.14	TOS map7	TOS Map 7	0x0000_0000
0x9C10803C0x9C10803C	G0.15	global que status	Global Queue Status	0x0000_00c0
0x9C1080400x9C108040	G0.16	addr tbl srch	Address Table Search	0x0000_0000
0x9C1080440x9C108044	G0.17	adr tblst	Address Table Status 0	0x0000_0000
0x9C1080480x9C108048	G0.18	MAC ad ser0	Address Table Status 1	0x0000_0000
0x9C10804C0x9C10804C	G0.19	MAC ad ser1	Address Table Status 2	0x0000_0000
0x9C1080500x9C108050	G0.21	wt mac ad0	wt mac ad0	0x0000_0000
0x9C1080540x9C108054	G0.21	w mac 15 0 bus	w mac 15 0 bus	0x0000_0000
0x9C1080580x9C108058	G0.22	w mac 47 16 bus	w mac 47 16 bus	0x0000_0000
0x9C10805C0x9C10805C	G0.23	PVID config0	PVID configure 0	0x0000_0000
0x9C1080600x9C108060	G0.24	Reserved	Reserved	0x0000_0000
0x9C1080640x9C108064	G0.25	VLAN member config0	VLAN member set config 0	0x0f0f_0f0f
0x9C1080680x9C108068	G0.26	VLAN member config1	VLAN member set config 1	0x0000_0f0f
0x9C10806C0x9C10806C	G0.27	port ability	port ability	0x0000_0000
0x9C1080700x9C108070	G0.28	port st	port status0x0000_0000
0x9C108074	G0.29	cpu cntl	CPU port control	0x0000_cfff
0x9C1080780x9C108078	G0.31	port cntl0	port control 0	0x0300_0303
0x9C10807C0x9C10807C	G0.31	port cntl1	port control 1	0x0000_0000
0x9C1080800x9C108080	G0.32	port cntl2	port control 2	0x8000_0300
0x9C1080840x9C108084	G0.33	sw glb cntl	switch global control	0x0004_a101
0x9C1080880x9C108088	G0.34	sw reset	Switch Reset	0x0000_0000
0x9C10808C0x9C10808C	G0.35	led port0	LED Port 0	0x8000_0615
0x9C1080900x9C108090	G0.36	led port1	LED Port 1	0x0000_0615
0x9C1080940x9C108094	G0.37	Reserved	Reserved	0x0000_0000
0x9C1080980x9C108098	G0.38	Reserved	Reserved	0x0000_0000
0x9C10809C0x9C10809C	G0.39	Reserved	Reserved	0x0000_0000
0x9C1080A00x9C1080A0	G0.41	watch dog trig rst	Watch dog trigger reset	0x7fff_0000
0x9C1080A40x9C1080A4	G0.41	watch dog stop cpu	Watch dog stop CPU port receiving	0x7fff_0000
0x9C1080A80x9C1080A8	G0.42	phy cntl reg0	PHY control register 0	0x0000_0000
0x9C1080AC0x9C1080AC	G0.43	phy cntl reg1	PHY control register 1	0x0000_0000
0x9C1080B00x9C1080B0	G0.44	mac force mode	MAC force mode0x0201_0000
0x9C1080B4VLAN	G0.45	VLAN group config0	VLAN group port config 0	0x0000_0f0f
0x9C1080B80x9C1080B8	G0.46	Reserved	Reserved	0x0000_0000
0x9C1080BC0x9C1080BC	G0.47	flow ctrl th3	Flow control threshold	0x0000_420c
0x9C1080C00x9C1080C0	G0.48	queue status 0	Queue status	0x0000_0000
0x9C1080C40x9C1080C4	G0.49	debug cntl	Debug control	0x0000_0000
0x9C1080C80x9C1080C8	G0.51	Reserved	Reserved	0x0000_0000
0x9C1080CC0x9C1080CC	G0.51	mem test info	Queue status	0xdead_dead
0x9C1080D00x9C1080D0	G0.52	sw int status 1	Interrupt Status 1	0x0000_0000
0x9C1080D40x9C1080D4	G0.53	sw int mask 1	sw int mask 1	0x0080_c0ff
0x9C1080D80x9C1080D8	G0.54	sw global signal	Global Control	0x0000_0000
0x9C1080DC0x9C1080DC	G0.55	Reserved	Reserved	0x0000_0000
0x9C1080E00x9C1080E0	G0.56	Reserved	Reserved	0xdead_dead
0x9C1080E40x9C1080E4	G0.57	Reserved	Reserved	0x0000_0000
0x9C1080E80x9C1080E8	G0.58	Reserved	Reserved	0x0000_0000
0x9C1080EC0x9C1080EC	G0.59	Reserved	Reserved	0x0000_0000
0x9C1080F00x9C1080F0	G0.60	Reserved	Reserved	0x0000_0000
0x9C1080F40x9C1080F4	G0.61	Reserved	Reserved	0x0000_0000
0x9C1080F80x9C1080F8	G0.62	Reserved	Reserved	0x0000_0000
0x9C1080FC0x9C1080FC	G0.63	Reserved	Reserved	0x0000_0000

Table 14-4 Switch Register Group 0

AddressAddress	Group No.	Register Name	Description	Reset Default
0x9C1082000x9C108200	G0.128	reserved	Reserved	0xdead_dead
0x9C1082040x9C108204	G0.129	Reserved	Reserved	0xdead_dead
0x9C1082080x9C108208	G0.130	cpu tx trig	CPU transmit trigger demand 0x0000_0000 demand
0x9C10820C	G0.131	Tx hbase ad 0	SoC port0 transmit high level priority descriptor base address	0x0000_0000
0x9C1082100x9C108210	G0.132	Tx lbase ad 0	SoC port0 transmit low level priority descriptor base address	0x0000_0000
0x9C1082140x9C108214	G0.133	Rx hbase ad 0	SoC port0 receive high level priority descriptor base address	0x0000_0000
0x9C1082180x9C108218	G0.134	Rx lbase ad 0	SoC port0 receive low level priority descriptor base address	0x0000_0000
0x9C10821C0x9C10821C	G0.135	Tx hw ad 0	SoC port0 transmit high level priority current working descriptor address	0x0000_0000
0x9C1082200x9C108220	G0.136	Tx lw ad 0	SoC port0 transmit low level priority current working descriptor address	0x0000_0000
0x9C1082240x9C108224	G0.137	Rx hw ad 0	SoC port0 receive high level priority current working descriptor address	0x0000_0000
0x9C1082280x9C108228	G0.138	Rx lw ad 0	SoC port0 receive low level priority current working descriptor address	0x0000_0000
0x9C10822C0x9C10822C	G0.139	cpu port cntl reg 0	SoC Port0 Control Register 0x0000_0000

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14.7.2 Registers Description

0.0 Interrupt Status Reg 0 (sw int status 0)
Address: 0x9C108000
Reset: 0x0

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Field Name	Bit	Access	Description
reserved	31:2	RO	RESERVED Reserved for further usage.
big endian	1	RW	Big endian mode AHB master bus endian mode. 1'b0: little endian; 1'b1: big endian.
sim mode	0	RW	Simulation mode This mode is used to speed up for simulation. 1'b0: normal mode; 1'b1: simulation mode.

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Field Name	Bit	Access	Description
reserved	31:0	RO	RESERVED Reserved for further usage.

0.128 Reserved (reserved)
Address: 0x9C108200
Reset: 0xdead dead

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Versions Compared

Old Version 27

New Version 28

Key

14.1 Introduction

14.7

Registers Map

14.7.1 Registers Memory Map

14.7.2 Registers Description