...
15.3 Interrupt type register3 (intr type[3])
Address: 0x9C00078C
Reset: 0x0003 C000
| Field Name | Bit | Access | Description |
| intr type[127:96] | 31:0 | RW | Determine interrupt type from bit 96 to 127 Different interrupt source has different default value. 0: level-type 1: edge-type |
...
| Field Name | Bit | Access | Description |
| intr type[159:128] | 31:0 | RW | Determine interrupt type from bit 128 to 159 Different interrupt source has different default value. 0: level-type 1: edge-type |
...
15.7 Interrupt polarity register0 (intr polarity[0])
Address: 0x9C00079C
Reset: 0x0000 0000 00FF
| Field Name | Bit | Access | Description |
| intr polarity[31:0] | 31:0 | RW | Determine interrupt polarity from bit 0 to 31 0: high-active(default) 1: low-active |
...
15.11Interrupt polarity register4 (intr polarity[4])
Address:0x9C0007AC
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| intr polarity[159:128] | 31:0 | RW | Determine interrupt polarity from bit 128 to 159 0: high-active(default) 1: low-active |
...
15.19 ACHIP priority register5 (ACHIP priority[5])
Address: 0x9C0007CC
Reset: 0xffff ffff
| Field Name | Bit | Access | Description |
| ACHIP priority[191:160] | 31:0 | RW | Determine ACHIP interrupt priority from bit 160 to 191 0: fiq(default) 1: irq |
...
15.23ACHIP interrupt mask register2 (ACHIP intr mask[2])
Address: 0x9C0007DC
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| ACHIP intr mask[95:64] | 31:0 | RW | Mask ACHIP interrupt from bit 64 to 95 0: masked(default) 1: pass |
...
15.27 ACHIP interrupt mask register6 (ACHIP intr mask[6])
Address: 0x9C0007EC
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Reserve | 31:8 | RO | |
| ACHIP intr mask[199:192] | 7:0 | RW | Mask ACHIP interrupt from bit 192 to 199 0: masked(default) 1: pass |
...
15.31 Reserve (rsv)
Address: 0x9C0007FC
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
| Reserve | 31:1 | RO | Reserve |
| Reserve | 0 | RW | Reserve |
...
21.3 ACHIP interrupt clear register3 (ACHIP intr clr[3])
Address: 0x9C000A8C
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
| ACHIP intr clr[127:96] | 31:0 | WO | Clear ACHIP interrupt from bit 96 to 127 |
...
21.7 Masked ACHIP FIQ register0 (masked ACHIP fiqs[0])
Address: 0x9C000A9C
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
| masked ACHIP fiqs[31:0] | 31:0 | RO | Read masked ACHIP fiqs from bit 0 to 31 |
...
21.11 Masked ACHIP FIQ register4 (masked ACHIP fiqs[4])
Address: 0x9C000AAC
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
| masked ACHIP fiqs[159:128] | 31:0 | RO | Read masked ACHIP fiqs from bit 128 to 159 |
...
21.15 Masked ACHIP IRQ register1 (masked ACHIP irqs[1])
Address: 0x9C000ABC
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
| masked ACHIP irqs[63:32] | 31:0 | RO | Read masked ACHIP irqs from bit 32 to 63 |
...
21.19 Masked ACHIP IRQ register5 (masked ACHIP irqs[5])
Address: 0x9C000ACC
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
| masked ACHIP irqs[191:160] | 31:0 | RO | Read masked ACHIP irqs from bit 160 to 191 |
...
21.20 Masked ACHIP IRQ register6 (masked ACHIP irqs[6])
Address: 0x9C000AD0
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
Reserve | 31:8 | RO RO |
|
...
21.27 Reserve (rsv)
Address: 0x9C000AEC
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
Reserve | 31:0 | WO |
...
21.31 Interrupt group register (intr group)
Address:0x9C000AFC
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
| Reserve | 31:23 | RO | |
| dsp intr group[6:0] | 22:16 | RO | Which interrupt group is triggered for DSP bit16: masked dsp intr[31:0] bit17: masked dsp intr[63:32] bit18: masked dsp intr[95:64] bit19: masked dsp intr[127:96] bit20: masked dsp intr[159:128] bit21: masked dsp intr[191:160] bit22: masked dsp intr[199:192] |
| Reserve | 15 | RO | |
| a926 irq group[6:0] | 14:8 | RO | Which interrupt group is triggered for ARM926 IRQ bit8: masked a926 irq[31:0] bit9: masked a926 irq[63:32] bit10: masked a926 irq[95:64] bit11: masked a926 irq[127:96] bit12: masked a926 irq[159:128] bit13: masked a926 irq[191:160] bit14: masked a926 irq[199:192] |
| Reserve | 7 | RO | |
| a926 fiq group[6:0] | 6:0 | RO | Which interrupt group is triggered for ARM926 FIQ bit0: masked a926 fiq[31:0] bit1: masked a926 fiq[63:32] bit2: masked a926 fiq[95:64] bit3: masked a926 fiq[127:96] bit4: masked a926 fiq[159:128] bit5: masked a926 fiq[191:160] bit6: masked a926 fiq[199:192] |
...