9. Interrupt Controller
9.1 Introduction
The SP7021 interrupt controller is a centralized resource for supporting and managing interrupts in a system. It provides low latency interrupt processing and efficient processing of arriving interrupts. Set registers for managing interrupt sources and interrupt behaviors. The interrupt mask, output FIQ/IRQ pins, trigger type and polarity all determined by register setting. The control registers locate at RGST Table Group15 and 21 which memory map are 0x9C000780~0x9C0007FF and 0x9C000A80~0x9C000AFF.
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9.2 Function Diagram
A generalized function diagram of interrupt controller is shown in Figure 9-1.
Figure 9-1 Interrupt Controller Functional Blocks
CPU GIC: ARM Cortex A7 generic interrupt controller.
INT_CTRL: Device interrupt controller. The interrupt source can come from internal device or external pins.
9.3 Interrupt Source
There are totally 200 interrupt sources defined in SP7021. They are listed in Table 9-1. The table also shows the interrupt trigger type and clock source for each interrupt. The interrupt trigger type can be selected as edge or level trigger, the control registers define in Group15.0~6.
No | Description | Hardware Name | Level/Edge Trigger | Clock Source |
|---|---|---|---|---|
0 | TEGN | TGEN_INT_FIELD_START | Edge | SYSCLK |
1 | TGEN | TGEN_INT_FIELD_END | Edge | SYSCLK |
4 | TGEN | TGEN_INT1_USER | Edge | SYSCLK |
5 | TGEN | TGEN_INT2_USER | Edge | SYSCLK |
10 | USBC1 | USBC1_OTG_INT | level | SYSCLK |
11 | USBC0 | USBC0_OTG_INT | level | SYSCLK |
13 | USBC0 | USBC0_DEVICE_INT | Level | SYSCLK |
14 | USBC0 | USBC0_EHCI_INT | Level | SYSCLK |
15 | USBC0 | USBC0_OHCI_INT | Level | SYSCLK |
16 | USBC1 | USBC1_DEVICE_INT | Level | SYSCLK |
17 | USBC1 | USBC1_EHCI_INT | Level | SYSCLK |
18 | USBC1 | USBC1_OHCI_INT | Level | SYSCLK |
20 | CARD0(EMMC) | CARD_CTL0_INT | level | SYSCLK |
21 | CARD1(SD) | CARD_CTL1_INT | level | SYSCLK |
22 | CARD_CTL4(SDIO) | CARD_CTL4_INT | Level | SYSCLK |
25 | RBUS | RBUS_INTERRUPT | Level | 200MHz |
28 | SECURITY | SDPROT_INT | Level | SYSCLK |
29 | From FPGA | PI_EXT0_INT | Level | SYSCLK |
30 | From FPGA | PI_EXT1_INT | Level | SYSCLK |
36 | UPHY0 | UPHY0_INT | Level | SYSCLK |
37 | UPHY1 | UPHY1_INT | Level | SYSCLK |
41 | IOP | IOP_INT0 | Level | SYSCLK |
42 | IOP | IOP_INT1 | Level | SYSCLK |
49 | MIPI | CSI0_INT_FIELD_START | Edge | SYSCLK |
50 | MIPI | CSI0_INT_FIELD_END | Edge | SYSCLK |
51 | MIPI | CSI1_INT_FIELD_START | Edge | SYSCLK |
52 | MIPI | CSI1_INT_FIELD_END | Edge | SYSCLK |
53 | UART0 | UA0_INT | Level | 27MHz |
54 | UART1 | UA1_INT | Level | 27MHz |
55 | UART2 | UA2_INT | Level | 27MHz |
56 | UART3 | UA3_INT | Level | 27MHz |
58 | BCH | BCH_INT | Level | SYSCLK |
59 | AUD | LOSD_INT | edge | SYSCLK |
60 | AUD | AUD_FIFO_INT | level | SYSCLK |
66 | Ethernet Switch | L2SW_INT | Level | SYSCLK |
67 | SPI_COMBO | SPI_COMBO_1_DMA_W_INT | Level | SYSCLK |
68 | SPI_COMBO | SPI_SLAVE_1_RISC_INT | Level | SYSCLK |
69 | SPI_COMBO | SPI_MASTER_1_RISC_INT | Level | SYSCLK |
70 | SPI_COMBO | SPI_COMBO_2_DMA_W_INT | Level | SYSCLK |
71 | SPI_1OMBO | SPI_SLAVE_2_RISC_INT | Level | SYSCLK |
72 | SPI_COMBO | SPI_MASTER_2_RISC_INT | Level | SYSCLK |
73 | SPI_COMBO | SPI_COMBO_3_DMA_W_INT | Level | SYSCLK |
74 | SPI_COMBO | SPI_SLAVE_3_RISC_INT | Level | SYSCLK |
75 | SPI_COMBO | SPI_MASTER_3_RISC_INT | Level | SYSCLK |
92 | Input Capture | ICM_INT0 | Edge | SYSCLK |
93 | Input Capture | ICM_INT1 | Edge | SYSCLK |
94 | Input Capture | ICM_INT2 | Edge | SYSCLK |
95 | Input Capture | ICM_INT3 | Edge | SYSCLK |
103 | AXI Global Monitor interrupt | AXI_MON_INT | level | 200MHz |
105 | HDMI_TX | HDMI_TX_INT | level | SYSCLK |
120 | Interrupt from analog | PI_GPIO_INT0 | Programmable | 27MHz |
121 | Interrupt from analog | PI_GPIO_INT1 | Programmable | 27MHz |
122 | Interrupt from analog | PI_GPIO_INT2 | Programmable | 27MHz |
123 | Interrupt from analog | PI_GPIO_INT3 | Programmable | 27MHz |
124 | Interrupt from analog | PI_GPIO_INT4 | Programmable | 27MHz |
125 | Interrupt from analog | PI_GPIO_INT5 | Programmable | 27MHz |
126 | Interrupt from analog | PI_GPIO_INT6 | Programmable | 27MHz |
127 | Interrupt from analog | PI_GPIO_INT7 | Programmable | 27MHz |
128 | CBDMA for System | CBDMA0_INT | Level | 200MHz |
129 | CBDMA for System | CBDMA1_INT |