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14.1 Introduction

Ethernet is a computer local area network technology. IEEE's IEEE 802.3 standard sets the technical standard for Ethernet, which specifies the content of the connection, electronic signal and medium access layer agreements including the physical layer. Ethernet is the most popular area network technology currently used, replacing other regional network standards such as Token Ring, FDDI and ARCNET. The standard topology of Ethernet is a bus topology, but the current fast Ethernet (100BASE-T, 1000BASE-T standard) used switch/hub in network connection and organization to increase the network speed, use efficiency and minimize conflicts. As a result, the topology of the Ethernet network becomes a star topology.
Ethernet implements the idea of transmitting information to multiple nodes in the radio system on the network. Each node must obtain cables or channels to transmit information. Each node has a globally unique 48-bit address, which is the MAC address assigned by the manufacturer to the network cardNetwork Interface Card (NIC). The MAC address is used to ensure that all nodes on the Ethernet can authenticate each other. Because Ethernet is so common, many manufacturers integrate Ethernet cards directly into their motherboards.
This section describes the Ethernet Switch and its associated operational modes. The SP7021 Ethernet is supports a layer 2 (L2) switch (L2SW) with 2 Ethernet ports and 1 SoC port (also called CPU port or NIC port) which acts as like a NIC card connected to the 3rd port of switch. The base address for Ethernet Switch Control and Status Registers (CSR) is 0x9C108000 and all registers in the memory map address ranges from 0x9C108000 to 0x9C10827F.
Table 14-1. shows the key feature of Ethernet hardware (L2SW IP) of SP7021.

switch ports

  • 2 IEEE802.3 10M/100M ports (port0 and port1)
    • 10M/100M with RMII  interface
    • Support half duplex and full duplex
    • Support full duplex flow control and half duplex back pressure
    • Embedded IP checksum hardware accelerator
    • Programmable receiving maximum packet size (1536 bytes, 1522 bytes or 1518 bytes)
    • Programmable port default priority
  • 1 SoC port
    • Support frame transmission and receiving from/to CPU by SoC port
    • Support frame forwarding between SoC port and the other 2 ports (port0 and port1)
    • Programmable CRC padding by hardware or software
    • Programmable SoC port MAC address and VLAN group
    • Descriptor based control/status exchange between CPU and the switch hardware
    • Embedded data/descriptor DMA engine
    • Programmable port default priority
    • Independent MAC address for independent driver used in NIC mode

VLAN

  • Programmable default VLAN group for each port
  • Programmable 6 VLAN groups and member sets of each VLAN group
  • Support VLAN priority

Address table

  • 1K MAC address table entries
  • Support both static filtering entries and dynamic filtering entries
  • Programmable address table addressing mode: direct or hash base on MAC address
  • Programmable aging enable or disable
  • Programmable aging time

QoS

  • Support 2 traffic class (compatible with IEEE802.1D-2004)

LED

  • Provide control lines for status LEDs ("link up/down" and "100M/10M")

Data buffer

  • Embedded 192k bits data buffer
  • Dynamic data buffer management

System interface

  • 32-bit AHB master interface as DMA bus
  • 32-bit AHB slave interface as register configuration bus

Table 14-1. Key feature of Ethernet Switch (L2SW IP) of SP7021

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14.3.1 Descriptors of Ethernet

Ethernet hardware The Layer 2 Switch (L2SW IP) uses descriptors to control transmission and reception of packets between CPU interface and L2 switch hardware2 Ethernet ports. Software allocates and initializes memory for descriptors. Descriptors consists of many fields which instructs Ethernet hardware where and how to get or store data for transmission and reception. The Ethernet hardware reads descriptors and uses the allocated memory to access data. Descriptors should be allocated continuously in the memory by software called descriptor queue and the Ethernet hardware uses these descriptors in order. Figure 14-2 illustrates the operation of descriptorsrelationship between descriptors and data buffers.

Figure 14-2 Descriptors of L2SW

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