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| A3 SWAP | 31:27 | RW | control DRAM A3 swap |
select one DRAM BUS signal to through DRAM A3 pin; | |||
default value is 0xc, represent DRAM A3 signal through | |||
DRAM A3 pin; | |||
0x0: select DRAM CKE signal through DRAM A3 pin; | |||
0x1: select DRAM ODT signal through DRAM A3 pin; | |||
0x2: select DRAM CS N signal through DRAM A3 pin; | |||
0x3: select DRAM RAS N signal through DRAM A3 pin; | |||
0x4: select DRAM CAS N signal through DRAM A3 pin; | |||
0x5: select DRAM WE N signal through DRAM A3 pin; | |||
0x6: select DRAM BA0 signal through DRAM A3 pin; | |||
0x7: select DRAM BA1 signal through DRAM A3 pin; | |||
0x8: select DRAM BA2 signal through DRAM A3 pin; | |||
0x9: select DRAM A0 signal through DRAM A3 pin; | |||
0xa: select DRAM A1 signal through DRAM A3 pin; | |||
0xb: select DRAM A2 signal through DRAM A3 pin; | |||
0xc: select DRAM A3 signal through DRAM A3 pin; | |||
0xd: select DRAM A4 signal through DRAM A3 pin; | |||
0xe: select DRAM A5 signal through DRAM A3 pin; | |||
0xf: select DRAM A6 signal through DRAM A3 pin; | |||
0x10: select DRAM A7 signal through DRAM A3 pin; | |||
0x11: select DRAM A8 signal through DRAM A3 pin; | |||
0x12: select DRAM A9 signal through DRAM A3 pin; | |||
0x13: select DRAM A10 signal through DRAM A3 pin; | |||
0x14: select DRAM A11 signal through DRAM A3 pin; | |||
0x15: select DRAM A12 signal through DRAM A3 pin; | |||
0x16: select DRAM A13 signal through DRAM A3 pin; | |||
0x17: select DRAM A14 signal through DRAM A3 pin; | |||
0x18: select DRAM A15 signal through DRAM A3 pin; |
15.4 Registers Map
15.4.1 Registers Memory Map
Address | Group No. | Register Name | Description |
|---|---|---|---|
0x9C001900 | G50.0 | dpcu glo set | DPCU Global Setting |
0x9C001904 | G50.1 | dpcu init ctrl | DPCU Initial control |
0x9C001908 | G50.2 | dpcu init status | DPCU Initial status |
0x9C00190C | G50.3 | dpcu aphy cnter | DPCU APHY Counter |
0x9C001910 | G50.4 | dpcu ddl calib set | DPCU DDL Calibration Global Setting |
0x9C001914 | G50.5 | dpcu sscpll ctrl1 | DPCU SSCPLL setting - 1 |
0x9C001918 | G50.6 | dpcu sscpll ctrl2 | DPCU SSCPLL setting - 2 |
0x9C00191C | G50.7 | reserved | DPCU Global reserved |
0x9C001920 | G50.8 | dpcu aphy glo | APHY - Global |
0x9C001924 | G50.9 | dpcu aphy macro0 | APHY - MACRO Status Output - 0 |
0x9C001928 | G50.10 | dpcu aphy macro1 | APHY - MACRO Status Output - 1 |
0x9C00192C | G50.11 | dpcu aphy mpll0 | APHY - MPLL 0 |
0x9C001930 | G50.12 | dpcu aphy mpll1 | APHY - MPLL 1 |
0x9C001934 | G50.13 | dpcu aphy ctcal0 | APHY - CTCAL 0 |
0x9C001938 | G50.14 | dpcu aphy ctcal1 | APHY - CTCAL 1 |
0x9C00193C | G50.15 | reserved | reserved |
0x9C001940 | G50.16 | dpcu aphy div | APHY - DIVIDER |
0x9C001944 | G50.17 | dpcu aphy ddl value | APHY - DDL Static DLY Value |
0x9C001948 | G50.18 | dpcu aphy iopad0 | APHY - IOPAD 0 PZQ |
0x9C00194C | G50.19 | dpcu aphy iopad1 | APHY - IOPAD 1 PZQ VREF |
0x9C001950 | G50.20 | dpcu aphy iopad2 | APHY - IOPAD 2 ADDR and CMD |
0x9C001954 | G50.21 | dpcu aphy iopad3 | APHY - IOPAD 3 DX |
0x9C001958 | G50.22 | dpcu aphy iopad4 | APHY - IOPAD 4 reserved |
0x9C00195C | G50.23 | dpcu aphy debug mode | APHY - DEBUG mode |
0x9C001960 | G50.24 | dpcu aphy osc mode | APHY - OSC mode |
0x9C001964 | G50.25 | dpcu aphy dummy port | APHY - DUMMY ports |
0x9C001968 | G50.26 | reserved | reserved |
0x9C00196C | G50.27 | reserved | reserved |
0x9C001970 | G50.28 | reserved | reserved |
0x9C001974 | G50.29 | reserved | reserved |
0x9C001978 | G50.30 | reserved | reserved |
0x9C00197C | G50.31 | reserved | reserved |
15.4.2 Registers Description
RGST Table Group 50DDR PHY-A Control Unit G1
50.0 DPCU Global Setting (dpcu glo set)
Address: 0x9C001900
Reset: 0x5432 AA21
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